IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 59, NO. 6, JUNE 2012 1607 Improved Methodology for Integrated k -Value Extractions Ivan Ciofi, Gianpaolo Borrello, Oreste Madia, Christopher J. Wilson, Bart Vereecke, and Gerald P. Beyer Abstract—We present an improved methodology for integrated k-value extractions that is based on the use of interconnect schemes with deep hanging low-k trenches and reduced passi- vation as a test vehicle. We perform a rigorous analysis for the calculation of the error bar and the evaluation of the impact of each source of uncertainty. We demonstrate the effectiveness of our methodology in reducing the error bar on the extracted integrated k-value at 90 nm half-pitch and discuss the limitations at narrow pitches. Index Terms—Damascene integration, dielectric constant, k-value, low-k dielectric materials. I. I NTRODUCTION N EW HIGHLY porous insulating materials with an ul- tralow relative dielectric constant (k-value) are being currently screened in order to identify the most promising candidates for next-generation Cu damascene interconnects [1]. The increased porosity makes these materials more prone to degradation during processing. Therefore, the impact of the damascene flow on the dielectric properties and, in particu- lar, on the k-value must be taken into careful consideration. Blanket wafers are commonly used for quick and cost-effective screening of low-k dielectrics and their compatibility with process steps, such as plasma etch or ash, chemical–mechanical polishing (CMP), and wet cleaning [2]. However, process con- ditions can be only partially reproduced on blanket wafers [3]. Hence, characterization on patterned wafers is finally required to qualify a certain material for a given technology node. The investigated material is integrated in Cu damascene structures, such as interdigitated interconnect capacitors, and the related postprocessing characteristics are evaluated [4]. In this conclu- sive phase, the accurate determination of the integrated k-value is fundamental for the estimation of the actual gain in inter- connect performance (RC delay) that can be achieved by the use of the new material. Based on the ITRS roadmap, the inte- grated k-value is expected to scale down by 0.2 with each new technology generation. Therefore, accuracy of at least ±0.1 is Manuscript received December 12, 2011; revised February 20, 2012; accepted March 8, 2012. Date of publication May 5, 2012; date of current version May 23, 2012. The review of this paper was arranged by Editor V. R. Rao. The authors are with the Imec, 3001 Leuven, Belgium (e-mail: Ivan.Ciofi@imec.be). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2012.2196436 Fig. 1. Schematic cross sections of the inspected interconnect schemes: (a) and (b) hanging low-k trenches of different depth; (c) landing low-k trenches on the SiCN etch-stop layer; and (d) shallow hanging oxide trenches, included as a control. The passivation consists of a thin layer of SiCN. required in order to be able to benchmark the new material against the existing ones from previous generation. The method for the evaluation of the integrated k-value is rather complex. In fact, the k-value is extracted from the measured line-to-line ca- pacitance by means of 2-D model simulations. The 2-D model is defined on the base of transmission electron microscopy (TEM) cross sections and realistic assumptions on the dielectric constants of the other layers in the damascene stack. The simulations are carried out by a 2-D static field solver in order to determine the dependence of the line-to-line capacitance on the k-value of the investigated low-k material. The integrated k-value is obtained by matching the model-based capacitance with the measured capacitance. Commonly, single-damascene structures are used as a test vehicle. In this case, the etch stop and passivation layers of a higher k-value will significantly con- tribute to the line-to-line capacitance [see Fig. 1(c)]. Therefore, small uncertainties on the dielectric constants and thicknesses of these parasitic layers will result in significant errors on the extracted k-value. Errors may also originate from a poor modeling of the line cross section, resulting, for instance, from a basic polygon approximation of an irregular trench profile. To the best of our knowledge, problems of accuracy in integrated k-value extractions have never been thoroughly investigated in literature. Furthermore, the error bar, which must be taken into account for fair comparisons between different low-k materials and processes, is typically not provided. In previous work, we reported on the accuracy limitations of industry standard procedures. As a result, an insufficient accuracy of ±0.3 was evaluated for integrated k-value extractions at 90 nm half-pitch for 2.2-2.5 low-k materials, when conventional damascene structures are used [5]. In this paper, we evaluated an unconventional interconnect scheme with deep hanging trenches as an optimized test ve- hicle for integrated k-value extractions [see Fig. 1(a)]. The 0018-9383/$31.00 © 2012 IEEE