Analog Integrated Circuits and Signal Processing, 36, 251–254, 2003 c  2003 Kluwer Academic Publishers. Manufactured in The Netherlands. Low-Voltage Rail-to-Rail Tunable FGMOS Transconductor I ˜ NIGO NAVARRO, ANTONIO J. L ´ OPEZ-MART ´ IN AND ALFONSO CARLOSENA Department of Electrical and Electronic Engineering, Public University of Navarra, Campus de Arrosadia, E-31006 Pamplona, Spain. Tel.: +34 948 169311; Fax: +34 948 169720 E-mail: antonio.lopez@unavarra.es Abstract. A compact, tunable CMOS transconductor is presented. The combined use of a Floating-Gate MOS (FGMOS) differential pair and a floating DC level shifter allows the use of low supply volatages while maintaining at the same time a rail-to-rail input range, low distortion and high linearity. Measurement results for a prototype fabricated using a 0.8 µm CMOS technology are provided, confirming on silicon the validity of the proposed approach. Key Words: CMOS transconductors, low-voltage analog circuits, analog CMOS circuits 1. Introduction Linear, tunable CMOS transconductors have found widespread use in today’s analog microelectronics, and several circuit topologies have been proposed. In order to achieve voltage-to-current conversion, they usually employ MOS transistors operating either in saturation or in ohmic (triode) region. In the first case, the MOS square law is usually exploited in such a way that lin- earization is achieved [1–3]. The second case corre- sponds to topologies that directly exploit the MOS V-I dependence in triode region for obtaining a linear V-I conversion [4–6], often leading to transconductors with higher linearity and increased tuning range. Some au- thors also combine both operating modes [7]. When rail-to-rail low-voltage operation is required, the design of the transconductor complicates notably. Simple differential pairs fail to keep a large input common-mode range, so that complementary PMOS and NMOS differential pairs are usually employed to overcome this issue. Unfortunately, rather complex auxiliary circuits need to be included to maintain a constant transconductance for any common-mode in- put in the complementary topology, thus notably com- plicating the circuit and increasing the power and area consumption. In this work a different approach will be em- ployed. Based on the transconductor presented in [8, 9], Floating-Gate MOS (FGMOS) transistors and floating DC-level shifters will be introduced in order to ob- tain a rail-to-rail transconductor operating at a single supply voltage V DD = V GS + 2V DS with a simple dif- ferential pair at the input, thus notably simplifying the resulting topology with regard to complementary input stages. 2. Circuit Description Figure 1(a) shows the proposed circuit. Starting from the topology presented in [8], the input differential pair is replaced by another one made by Floating-Gate MOS (FGMOS) transistors. In these transistors, inputs are capacitively coupled to the gate, which is therefore left floating. Due to the capacitive voltage division at the input gates (accurately determined by the ratios of the input capacitance values), the input range is extended [10]. A floating DC level shifter V B (floating battery) is included in the upper current mirror so that the require- ments for the maximum voltage in the low-impedance input of the current-mirror are relexed notably. As a re- sult, the topology features a rail-to-rail input common- mode range at a low supply voltage. The negative feedback of amplifiers A 1 and A 2 sets the drain voltage of the differential pair transistors to V BIAS 1 (an external control voltage). If V BIAS 1 is set such that transistors M i (i = 1, 2) operate in triode region, and assuming that V SS = 0 V, their drain currents will