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Zhao, Fellow, IEEE Abstract—The arguments presented in the above comments are refuted. The following are pointed out: 1) Veliadis’ papers did not include the vertical-junction field-effect transistor (VJFET) dimensions required for readers to make technical analysis and comparison. 2) The current through the gate p-n junction of a VJFET is also affected by the ohmic contact and metal spreading resistance; therefore, the external gate terminal voltage alone does not determine whether a VJFET is operated in bipolar mode or not. 3) A longer vertical channel with a more invariant or uniform vertical-channel opening makes it much easier to realize higher performance and higher voltage normally-off JFETs because of the lower channel resistance and the larger drain voltage needed to punch through the drain-to-source barrier. Index Terms—Junction field effect transistors (JFET), normally-off, normally-on, power transistors, silicon carbide, vertical channel. Of primary importance, as Veliadis stated in his Comments, is that we failed to cite selected SiC vertical-junction field-effect transistor (VJFET) power-switching device bibliography [1]–[6]; as such, our claim of record-high performance is dubious. It should be pointed out that the papers by Veliadis et al. [1]–[6] were not cited as they did not contain device dimensions that are required for technical analysis and comparison. Specifically, all of the papers listed as references in Veliadis’ Comments include only wafer information and final device data; there was no information on the channel width, channel pitch, channel implantation dose or energy, edge termination guard ring dimensions, or edge termination implantation dose or energy. There is nothing dubious in our statement that “The R SP-ON values of 1.75 mΩ · cm 2 at V GS = 3 V and 2.0 mΩ · cm 2 at V GS = 2.5 V are the lowest among all 1500-V-class normally-on SiC FETs reported to date.” The lowest R SP-ON reported by Veliadis is 2.1 mΩ · cm 2 , which is not measured at V GS = 2.5 V but at V GS = 3.0 V, as clearly shown in his paper [1]. The R SP-ON values that were clearly reported and stated as measured at V GS = 2.5 V by Veliadis include the following: 5.6 [7], [8], 5.3 [4], and 5.5 mΩ · cm 2 [5]. Following are more specific responses to each of his comments. 1) In his Comments, Veliadis cited his papers, i.e., his references [2]–[4], as sources that reported the fabrication of VJFETs by stepper photolithography, instead of e-beam lithography. However, none of these three papers, which are cited here as [4], [5], [7], and [8], mentioned the lithographic technique used in the fabrication of the reported VJFETs. 2) In his Comments, Veliadis disagrees with our statement that the vertical channel of a static induction transistor (SIT) does not have a highly uniform channel width and presented histograms Manuscript received June 10, 2009; revised August 23, 2010; accepted September 7, 2010. Date of publication October 21, 2010; date of current version November 19, 2010. The review of this paper was arranged by Editor M. Anwar. Y. Li is with the Elecronic Devices Institute, Nanjing 210000, China. P. Alexandrov is with United Silicon Carbide, Inc., Monmouth Junction, NJ 08852 USA. J. H. Zhao is with SiCLAB, Rutgers University, Piscataway, NJ 08854 USA (e-mail: jzhaoece@gmail.com; jzhao@ece.rutgers.edu). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2010.2079190 0018-9383/$26.00 © 2010 IEEE