Fundamentals and extraction of velocity saturation in sub-100nm (110)-Si and (100)-Ge L.Pantisano, L.Trojman*, J.Mitard, B. DeJaeger, S.Severi, G.Eneman, G.Crupi + , T.Hoffmann, I.Ferain*, M.Meuris, M.Heyns* IMEC Kapeldreef 75 Leuven (Belgium), also *KU Leuven, + Univ. Messina, email pantisan@imec.be Abstract A novel RFCV-technique is applied to directly quantify the short channel devices at high V ds , enabling parameter extraction like velocity saturation and critical field. This technique is applied to benchmark Si (110) and Si(100) as well as Ge devices. Similarities and crucial differences between short channel parameters in Si and Ge are discussed. Introduction: mobility, velocity and short channel devices Novel dielectric materials on Si or alternative substrates (Ge, GaAs,…) are typically benchmarked by using the long channel mobility u eff in linear regime (V ds =50mV) and the I ON -I OFF for short channel devices (V ds ≥ 1V) in saturation conditions. For any gate length I ON /W=v*Q inv , where Q inv is the charge in the inversion layer and v the carrier velocity. High mobility u eff is desirable since u eff and v (i.e., I ON ) are linked, at least at low lateral field E lat where v ~ u eff *E lat . However when E lat >E critical the v starts to saturate [1,2] and u eff is no longer a good metric for performances. More in general short channel parameters like metallurgical length (L met ), v sat and mobility u eff at operating conditions (V ds ≥ 1) would better describe the device physics and enable a proper comparison between different materials: this fundamental link is still missing for novel substrate materials like Si-(110) and Ge. We previously reported [3] a technique to extract the short channel electrostatics (L met and series resistance R series ) and mobility down to 50nm lengths. This paper expands on the previous methodology and uses an original RFCV technique to extract saturation velocities and critical fields at high V ds for short channel devices. The fundamental link between v sat and u eff for 1.2nm EOT MOSFETs on Si ((100) and (110)) and Germanium is reported and benchmarked. Device fabrication Conventional CMOS65 with 1.2nm SiON/poly-Si down to L poly =50nm were considered as reference. Using the same doping as CMOS65, N- and PFET were fabricated on the same wafer with the same dielectric and gate electrode (HfSiON/TiN) with L gate ~70nm on both Si-(100) and Si(110) wafers [4]. Finally planar Ge pFET were considered [5] with L gate down to 120nm with Si-passivation layer and HfO 2 /TaN gate stacks. Note that these devices were not optimized for best performance. Short channel parameters at high V ds Key information on Ge short channel parameters can be extracted from CV measurements, as in fig.1-3. Following a procedure developed for standard poly-Si/SiON [3], good short channel behavior can be demonstrated for our Ge samples (fig.1) with high mobility (fig.2). Similar high mobility (200cm²/Vs) to the ones of fig.2 was already reported [4] for (110)-Si pFET. Note in Fig.3 the lower R series for Ge devices and a similar mobility between pFETs on Ge(100) and Si(110). Once the basic short channel properties are known (i.e., fig.1-3), the transport properties at high V ds can be done, as discussed in fig.4-6. The inversion capacitance C inv can be determined for all V ds conditions (fig.4) and all the L met (fig.5) of interest using the procedure of Fig.6. Note in fig.5 that the C inv is L met dependent due to charge sharing. Since this is important only for L met <100nm, in the following C inv will be assumed L- independent. After R series normalization, the u eff = I ds L met /V ds WQ inv and v sat = I ds /WQ inv , where Q inv is the inversion charge (i.e., integration of C inv in fig.4-5). Contrary to previous v sat -extraction proposed [2], [6], this technique is direct and enables a simultaneous evaluation of both u eff and v sat in any bias condition (i.e., V gs , V ds ). Velocity saturation in Si (110) and Ge In fig.7 the v sat vs E lat is compared for HfSiON on Si(100) and Si(110). Note v sat (110)pFET ~ v sat (100)nFET. Since the doping and the gate stack are the same, the v sat increase is due to the Si orientation itself. Fig.8 also demonstrates that Ge features a 2x higher v compared to reference pFET on (100). In the following we approximated E lat =V ds /L met . This is somewhat a crude approximation, as confirmed by process and device calibrated TCAD simulation (not shown) where the point-to- point field along the channel can increase up to 10x close to the drain (especially in long channels). However it can be shown that the v sat -E lat trend shown in fig.7 for the SiON/poly-Si is correct and thus the v sat and E lat should be considered as mean values. Mobility and critical field – a perspective For the first time the u eff vs. E lat in fig.9 and 10 shows fundamental similarities and differences between Si and Ge. Similar to Si [1,7], also for Ge the critical field E critical concept is applicable. At low E lat the u eff is constant (i.e., Ohm’s law), while at E lat >E critical u eff decreases (i.e., v starts to saturate – see fig.7,8). An important difference between the high mobility Si (i.e., (110)- pFET) and Ge samples is that for E lat >E critical u eff decreases faster for Ge compared to Si. A combined analysis of fig.7-10 demonstrates the advantage of these novel techniques for benchmarking high mobility substrates. When the pFET on Si (110) and Ge are considered (see fig.11), the I ON on these devices should be similar (for a given CET) since v sat is the same. However when the ON-OFF switching is concerned (see fig.12), the u eff (Ge) decreasing faster with E lat (compared to Si) implying that the velocity saturates at a lower E lat thus yielding a slower switching speed. While it’s not clear whether these properties of Ge pFETs are linked to the fabrication process (possibly related to the S/D region germanidation) or a fundamental limit of the Ge itself, these pFET in Si-(110) seem superior to these Ge samples. Summary and Conclusions A direct extraction of velocity and mobility at high V ds for sub- 100nm MOSFETs has been demonstrated using a modified RFCV technique. This technique enables the benchmarking of very different MOSFET technologies (Ge and Si(110)) with respect of carrier velocity and mobility. Saturation velocities are very similar for pFET Ge and pFET Si (110), suggesting similar I ON drivability (2x compared to pFET on Si(100)). However Ge samples seem to reach velocity saturation at lower lateral fields thus possibly limiting the switching speed. References [1] Taur, Ning, Fundamentals of Modern VLSI devices, Cambridge Press 1998; [2] Sodini et al TED 1984; [3] Severi et al, TED 2007; [4] L.Trojman et al, INFOS 2007; [5] G.Nicholas, TED 2007 p.2503; [6] Lochtfeld, Antoniadis EDL 2001 p95; [7] Coen, Muller, Sol. State El. 23 p35-40; [8] E. San Andrés, EDL 2006; 978-1-4244-1805-3/08/$25.00 © 2008 IEEE 2008 Symposium on VLSI Technology Digest of Technical Papers 52