© 2003 ICECE March 16 – 19, 2003, São Paulo, BRAZIL 3 rd International Conference on Engineering and Computer Education 1 A Reconfigurable Architecture for Multi-Context Application Manoel E. de Lima 1 , Remy E. Sant’Anna 2 , Abel G. Filho 1 , Abner Barros 1 , Paulo Guedes 1 , Julio A. Filho 1 , Raimundo Barreto 1 and Claudianne Rabelo 1 Abstract  A reconfigurable computer presents the facil- ity of changing functions according to the lacks of the application. Based on reconfigurable devices, this ap- proach can reduce costs, especially in terms of hardware implementation. The developing of platforms with recon- figurable hardware and programmable control devices, can be used in several applications as in a hard- ware/software codesign approach, for small and large designs. This work describes an implementation of a multi- context system in a reconfigurable environment. The plat- form description is presented, as well as the reconfigura- tion method. A biological application has been developed using the proposed platform. Satisfactory results have been reached and are described in this paper. Key words: Reconfigurable Computing, FPGA, Microcon- trollers,Hardware/Software Codesign, Biological Applica- tions. Introduction Traditional electronic computing presents two methods for the execution of algorithms. The first uses ASICs (Ap- plication Specific Integrated Circuits) to perform the op- erations in hardware. Once time it is developed for a spe- cific computation, it’s very fast and efficient. However, cannot be modified for another application. This forces a re-design of a new chip, for a new functionality, in an expensive process. Software approaches present advantages such as flexi- bility and low cost for implementation of complex func- tions. However, it presents limitations, such as difficult to explore parallelism and high speed applications. These processes are implemented in devices such as microproc- essors and microcontrollers. On the other hand, reconfigurable computing is in- tended to fill the gap between hardware and software, achieving potentially much higher performance than soft- ware, while maintaining a higher level of flexibility than hardware [5],[6],[13]. This work aims the prototyping of a multi context problem in a reconfigurable platform called Chameleon. This platform allows, into a hw/sw codesign methodol- ogy the rapid prototyping of digital systems in a single or multi context approach. Chameleon’s functionality and the way a multi context design is implemented on it are pre- sented. Particularly a biotechnology application focusing biosensors will be described in details as a case study. Such architectures and devices has been developed and applied in several areas such as image processing, digital signal processing, electronic, audio and video applications, biotechnology, and so on. In this paper, a brief description of Chameleon prototyping board architecture is presented in section 2. The proposed methodology and design flow for multicontext prototyping is covered at section 3. Section 4 describes the platform monitor program. A biological application, for monitoring a piezoelectric bio- sensor is presented as a case study in section 5 in order to demonstrate the methodology. Final conclusions are pre- sented in section 6. Architecture Overview The Chameleon architecture [15] comprises a prototyp- ing board and CAD tools that help the designing and test- ing of digital systems. The basic prototyping board is composed of a software and a hardware component that share a common memory and a communication channel, as depicted in Figure 1. Software processes are executed in a low coast off-the- shelf microcontroller, 8051-compatible family[16]. It can run processes using an ad hoc approach or yet using run- time kernels to provide more functionality to the system, e.g. the Tiny Real Time Operating System from Keil Inc [2], [4]. The hardware processes are implemented on a single reconfigurable array element based on a subset of the XC4000 Xilinx Series [1]. This subset can support circuits between 3000 to 13000 equivalent Xilinx gates, depending on the chip part [10]. Two memory banks, composed of a 64 Kbytes program memory and a 64 Kbytes data memory provide storage space to keep the FPGA configuration and microcontroller program as well as variables and any dynamic process information. 1 Manoel E. de Lima, Centro de Informática, Universidade Federal de Pernambuco, Cidade Universitária, Recife, PE, Brazil, mel@cin.ufpe.br 2 Remy E. Sant’Anna, Universidade de Pernambuco – Escola Politécnica Rua Benfica 455 Madalena, Recife-PE res@cin.ufpe.br 1 Abel G. Filho, Centro de Informática, Universidade Federal de Pernambuco, Cidade Universitária, Recife, PE, Brazil, agsf@cin.ufpe.br 1 Abner Barros, Centro de Informática, Universidade Federal de Pernambuco, Cidade Universitária, Recife, PE, Brazil, acb@cin.ufpe.br 1 Paulo Abadie Guedes, Centro de Informática, Universidade Federal de Pernambuco, Cidade Universitária, Recife, PE, Brazil, pag@cin.ufpe.br 1 Julio A. Filho, Centro de Informática, Universidade Federal de Pernambuco, Cidade Universitária, Recife, PE, Brazil, jaof@cin.ufpe.br 1 Raimundo Barreto, Centro de Informática, Universidade Federal de Pernambuco, Cidade Universitária, Recife, PE, Brazil, rsb@cin.ufpe.br 1 Claudianne Rabelo, Centro de Informática, Universidade Federal de Pernambuco, Cidade Universitária, Recife, PE, Brazil, cmr@cin.ufpe.br