Published: May 10, 2011 r2011 American Chemical Society 2272 dx.doi.org/10.1021/nl200449v | Nano Lett. 2011, 11, 2272–2279 LETTER pubs.acs.org/NanoLett A Complete Fabrication Route for Atomic-Scale, Donor-Based Devices in Single-Crystal Germanium G. Scappucci,* ,†,‡ G. Capellini, § B. Johnston, || W. M. Klesse, †,‡ J. A. Miwa, †,‡ and M. Y. Simmons †,‡ † School of Physics, University of New South Wales, Sydney, NSW 2052, Australia ‡ Australian Research Council Centre of Excellence for Quantum Computation and Communication Technology, University of New South Wales, Sydney, NSW 2052, Australia § Dipartimento di Fisica, Universit  a di Roma Tre, Via della Vasca Navale 84, 00146 Roma, Italy ) Macquarie University, Department of Physics, MQ Photon, North Ryde, NSW 2122 Australia b S Supporting Information A s device miniaturization approaches the 16 nm technology node, the semiconductor industry looks to integrate alter- nate high mobility materials into the Si platform for faster transistor operation with lower dissipation. 1 Ge is appealing due to its high mobility and small band gap with the promise to produce transistors with higher operation speed, better scaling, and reduced power. 2,3 Besides its use in classical ultrascaled devices, Ge is also attractive for quantum information pro- cessing. 4 It shares with Si the possibility of long electron spin coherence times and isotope purification. In addition, the Bohr radius of donor-bound electrons in Ge (64 Å) is larger compared to Si (25 Å). The greater extent of the electron wave function will allow for greater spacing between solid-state qubits thereby relaxing lithographic requirements. Even though the first transistors were built using Ge, progress in Ge-based electronics has historically been hindered by the relatively high cost of Ge substrates and the lack of a stable native oxide for use as a high-quality gate dielectric. Today, however, these issues have been surmounted following the maturity of high-k dielectrics technology compatible with Ge, 2 and the integration of Ge onto Si substrates within the CMOS fabrication process. 5 The 2009 International Technology Roadmap for Semiconductor acknowledges this potential: Ge is ranked, among the other candidate materials as IIIÀV, nanotubes, and graphene, as the high mobility material option with the most favorable integration perspective into the Si platform. 1 In fact, recent progress in Ge-based electronics has led to high-quality p-type field effect transistors fabricated with traditional top-down architectures that incorporate Ge oxynitride 6 or hafnium oxide 7 as a gate dielectric. Alternatively, novel architectures based on bottom-up concepts have been used to fabricate Ge/Si core/shell nanowire field-effect transistors 8 that have out-performed state- of-the-art Si MOSFETs. 9 This approach has also been used to create tunable double quantum dots in Ge/Si heterostructure based nanowires. 10 Such promising results have prompted the quest for radical new strategies for fabricating planar atomically precise electronic devices in Ge. An atomic-scale device fabrication scheme for Si has already been successfully implemented. 11 With this approach, atomic- scale devices are defined by abrupt changes in the density of phosphorus donors embedded in the Si crystal. Laterally pat- terned phosphorus-doped δ-layers first proposed by Tucker et al. 12 are created in ultrahigh vacuum (UHV) using a combina- tion of scanning tunneling microscopy (STM) hydrogen litho- graphy, gas phase doping from phosphine (PH 3 ), and low temperature molecular beam epitaxy (MBE). To date, this STM fabrication technology has progressed from the early stages of fabricating individual nanoelectronic components, such as nanowires and tunnel junctions, 13 to the development of a full donor-based device architecture. This fabrication method has Received: February 7, 2011 Revised: May 5, 2011 ABSTRACT: Despite the rapidly growing interest in Ge for ultrascaled classical transistors and innovative quantum devices, the field of Ge nanoelectronics is still in its infancy. One major hurdle has been electron confinement since fast dopant diffusion occurs when traditional Si CMOS fabrication processes are applied to Ge. We demonstrate a complete fabrication route for atomic-scale, donor-based devices in single-crystal Ge using a combination of scanning tunneling microscope lithography and high-quality crystal growth. The cornerstone of this fabrication process is an innovative lithographic procedure based on direct laser patterning of the semiconductor surface, allowing the gap between atomic-scale STM-patterned structures and the outside world to be bridged. Using this fabrication process, we show electron confinement in a 5 nm wide phosphorus-doped nanowire in single-crystal Ge. At cryogenic temperatures, Ohmic behavior is observed and a low planar resistivity of 8.3 kΩ/0 is measured. KEYWORDS: Germanium, laser, nanostructures, doping, scanning tunneling microscope, nanowire