A Pipelined ADC Design Exploration Methodology Employing Circuit-System Refinement Mahmoud Abdoallah (1) , Mohamed Dessouky (2,3) , Marie-Minerve Louërat (3) , Hugo Gicquel (4) and Abdel Halim Shousha (1) (1) University of Cairo, Egypt, (2) University of Ain Shams, Egypt, (3) LIP6 Laboratory, Université Pierre & Marie Curie, France (4) STMicroelectronics, Grenoble, France Abstract — A pipelined ADC equation-based design space exploration methodology targeting minimum power dissipation is presented. While distinct frontiers are drawn between system- level and circuit-level design phases, this paper shows the importance of a refinement step between both phases. At the system-level, all possible architectures are examined followed by behavioral validation. Using a circuit sizing tool, different circuit topologies are investigated. The refinement phase proves to be important to increase the accuracy of system-level calculations by remapping new circuit-related parameters using the achieved circuit performances. The flow was built in an open system environment where the user has the freedom to change the modeling approach at any level, introduce different equations, and relax/tighten design constraints. An 11-bit ADC design test case is given to illustrate the methodology. I. INTRODUCTION Pipelined ADC design process includes a lot of design variables starting from the system level down to physical layout. Figure 1 shows a generic pipelined ADC composed of K stages each with a resolution of ni bits. The traditional design way reduces the design problem to a single stage one and simply clones this stage, with proper scaling, to form the complete converter. Different analog synthesis tools have addressed the problem using a similar approach [1]. It can be shown that vast performance enhancements can be achieved by investigating all different bit distributions along the ADC and by scaling the constraints along the pipeline in a system design phase [2, 3]. In this work, a system design refinement phase is introduced. Achieved circuit parameters are injected back to a system parameter mapping phase till reaching predefined performance accuracy. This is opposed to a rigid top-down methodology, where circuit blocks are over-constrained which may lead to increased power consumption. Refinement increases calculation accuracy and enables overall design optimization. This paper is organized as follows; in section II the general flow is outlined. In section III, system-level design is discussed, followed by the circuit-level design phase in section IV. Section V illustrates the refinement phase. Finally a design example with simulation results is presented in section VII. Figure 1. Pipelined ADC with K stages II. PROPOSED FLOW WITH REFINEMENT The outline of the top-down flow is presented in figure 2. Both system and circuit level design phases uses a three-step flow [1]. Each level i produces the specifications of the following level S(i+1) through the following phases: 1. Architecture Selection/Exploration “E(i)” At this step all possible/feasible architectures at level i are generated. At the system level they are all the possible bits/stage distributions. In figure 1 this means changing n 1 ,n 2 ,..n k . On the circuit level, different circuit topologies and technologies are examined. 2. Specification Mapping “M(i)” Uses an equation-based approach at both system and circuit levels to interpret level i specs to the lower level i+1. 3. Verification “V(i)” Uses simulation to examine achieved performances at level i versus S(i) specifications. A different architecture might be chosen by going back to exploration, E(i) . Figure 2. Proposed flow with refinement