1056 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 7, JULY 2004 A 70-mW 300-MHz CMOS Continuous-Time ADC With 15-MHz Bandwidth and 11 Bits of Resolution Susana Patón, Antonio Di Giandomenico, Luis Hernández, Member, IEEE, Andreas Wiesbauer, Member, IEEE, Thomas Pötscher, and Martin Clara Abstract—A wide-bandwidth continuous-time sigma-delta ADC is implemented in a 0.13- m CMOS. The circuit is tar- geted for wide-bandwidth applications such as video or wireless base-stations. The active blocks are composed of regular threshold voltage devices only. The fourth-order architecture uses an OpAmp-RC-based loop filter and a 4-bit internal quantizer operated at 300-MHz clock frequency. The converter achieves a dynamic range of 11 bits over a bandwidth of 15 MHz. The power dissipation is 70 mW from a 1.5-V supply. Index Terms—Analog–digital conversion, continuous-time fil- ters, delta-sigma modulation, low-pass filters, low-voltage design, sigma-delta modulation. I. INTRODUCTION M ANY APPLICATIONS in the consumer market and also in the area of wireless base stations require analog-to-digital converters (ADCs) with bandwidths up to 20 MHz and resolutions of 10–12 bits. Such systems are often accompanied by highly complex digital circuitry, which requires an implementation in a deep-submicron technology. Typically, for such requirements, subranging or pipeline ADCs are employed [1]–[3]. In this paper, we discuss the possibility of building a sigma-delta ADC for those applications and show the potential benefits compared to other ADC architectures. For discrete time (DT) modulators, implemented in switched-capacitor technique, the bandwidth is typically limited to less than 2 MHz [4], [5]. However, attempts have been reported to enlarge the bandwidth of ADCs by going from switched-capacitor (SC) circuits to continuous-time (CT) circuits [6], [7], achieving 3-MHz and 6-MHz bandwidth. In [8], a CT ADC was reported to have a bandwidth of 12 MHz. Modern CMOS processes allow the efficient design of high-resolution SC ADCs with a maximum sampling rate of approximately 100–150 MHz—a factor of 7 below the gain-bandwidth product (GBW) achievable for operational amplifiers (OpAmps). For CT ADCs, the ratio between GBW and sampling frequency is much lower—approximately two [9], [10]. Hence, if these same OpAmps were used in a Manuscript received November 10, 2003; revised January 20. 2004. S. Patón and L. Hernández are with Universidad Carlos III de Madrid, E-28911 Madrid, Spain (e-mail: spaton@ing.uc3m.es). A. Di Giandomenico, A. Wiesbauer, T. Pötscher, and M. Clara are with In- fineon Technologies Austria, A-9500 Villach, Austria (e-mail: antonio.digian- domenico@infineon.com) Digital Object Identifier 10.1109/JSSC.2004.829925 CT modulator, they could allow a sampling rate of 400 MHz and above. Thus, it is indeed feasible to build high-reso- lution CT ADCs with a bandwidth of 20 MHz and beyond. This approach leads to more power- and area-efficient ADCs as compared to pipeline or subranging type converters of equivalent resolution and bandwidth. Besides the advantage of CT circuitry with respect to higher bandwidth and/or power dissipation, there are some difficul- ties to overcome when designing such an ADC. First, the de- velopment of a suitable architecture is more problematic than in an SC design approach since the CT components show a higher variation with process, temperature, and supply-voltage spread. Second, the CT feedback circuitry leads to a less stable loop due to the inherent delay of the internal current-steering digital-to-analog converters (DACs). Finally, the internal cur- rent-steering DAC is much more susceptible to clock jitter than its SC counterpart. All these major issues are extremely critical when it comes to high-bandwidth A/D conversion [9], [10]. Sub- sequent sections of this paper address these issues and solutions for the problems are presented. II. SYSTEM-LEVEL CONSIDERATIONS A. System Overview The target specification for the ADC described in this paper was defined to be 11 bits with a maximum power dissipation of 100 mW. Optimization of the design was requested such that the achievable bandwidth is at least 12 MHz Fig. 1 shows a block diagram of a general CT modulator. At system level, the resolution achieved by such a system is a function of the oversampling ratio (OSR), noise-shaping order ( ) and quantizer resolution ( ) [11]. (1) In the present design, an OSR has been chosen as a compromise between a technologically feasible clock frequency and the robustness requirement. Once this parameter was estab- lished, the noise shaping was set to fourth order and the quan- tizer resolution to 4 bits. These parameters were selected to obtain the dynamic range (DR) well above the required limit. This allows the noise transfer function (NTF) of the CT modu- lator to be adapted to a more robust design at the expense of a lower DR. 0018-9200/04$20.00 © 2004 IEEE