Cross-Connected Intermediate Level (CCIL) Voltage Source Inverter Toufann Chaudhuri, Peter Barbosa Peter Steimer Alfred Rufer Power Electronic Applications Power Electronics and MV drives Laboratoire d’Electronique Industrielle ABB Corporate Research Centre ABB Schweiz AG Ecole Polytechnique Fédérale de Lausanne 5405 Baden-Dättwil, Switzerland 5300 Turgi, Switzerland 1015 Lausanne, Switzerland Abstract – Recently, multilevel applications have known many improvements. Initially introduced to answer the problem of the series-connection of components in medium voltage applications, multilevel topologies have now to serve new purposes. Recent multilevel technologies have the potential to significantly reduce the size of passive filters, thus increasing efficiency and power density. With the more stringent regulations concerning harmonic emissions, more levels are needed to allow filterless operation while keeping a moderate switching frequency. In this context, the new topological family of high density advanced multilevel inverters, called cross-connected intermediate level (CCIL) voltage source inverter, is introduced in this paper and offers a novel solution to generate multiple output levels. I. INTRODUCTION Since the first introduction of multilevel topologies in the early 1980’s [1], [2], new topological families, like the flying capacitor [5], [6] or the cascaded H-Bridge [3], [4] have been proposed with more or less impact on the industry. Reliability, complexity or costs of these new structures have often been questioned, as increased number of levels calls for increased number of components. This paper proposes a novel topological family called Cross Connected Intermediate Level (CCIL) voltage source inverter. The aim is to offer new possibilities to build increased number of levels in voltage source inverters while trying to keep the number of components as reduced as possible. II. GENERAL TOPOLOGY The introduced topology shown in Fig. 1 is a modular structure consisting of three different stages: A, B and C. The first stage, A, is a 3 level ANPC structure [8]. The second stage, B, is the so called cross-connected stage. It consists of one phase capacitor connected through two bidirectional and two unidirectional switches, mounted in a crossed configuration. This stage can be cascaded in series or in parallel as many times as wanted, generating an exponential amount of levels. The final stage, C, consists of two unidirectional switches connecting the inverter to the output phase. The cross-connected stage B allows connecting the two output poles of each stage (3 and 4 in Fig. 2), in every possible way, to the two input poles (1 and 2 in Fig. 2) through the phase capacitor, therefore allowing subtracting and/or adding the capacitor’s voltage to both inputs in every possible way. The dipole equations for the cross-connected intermediate levels can be written down as V 3 = [V 1 ;V 1 –U cf1 ;V 2 ;V 2 –U cf1 ] and V 4 = [V 1 ;V 1 +U cf1 ;V 2 ;V 2 +U cf1 ]. The capacitor voltage ratio with respect to the dc link voltage will determine the number of redundant output levels, and whether the steps between levels will be uniform or not. In a general case, the total amount of paths P(n) through the inverter is given by (1), where n is the amount of stages (n=2 in Fig. 1). P(n) = 16·3 n-1 (1) Among all the possible paths, the zero and both DC voltages will be redundant multiple times. If these redundancies are eliminated, the resulting possible paths are called the switching states S(n). S(n) = 3 n+1 (2) Depending on the choice of the capacitor voltage ratios, a certain amount of redundancies will appear on the switching states concerning the output voltage. Figure 1: General topology of the CCIL voltage source inverter Figure 2: Dipole view of one stage, inputs are 1 and 2, and outputs are 3 and 4. 490 1-4244-0655-2/07/$20.00©2007 IEEE