Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture Gert Jervan, Petru Eles, Zebo Peng Embedded Systems Laboratory (ESLAB) Linköping University, Sweden {gerje, petel, zebpe}@ida.liu.se Raimund Ubar, Maksim Jenihhin Department of Computer Engineering Tallinn Technical University, Estonia {raiub, maksim}@pld.ttu.ee Abstract 1 This paper presents a solution to the test time minimization problem for core-based systems that contain sequential cores with STUMPS architecture. We assume a hybrid BIST approach, where a test set is assembled, for each core, from pseudorandom test patterns that are generated online, and deterministic test patterns that are generated off- line and stored in the system. We propose a methodology to find the optimal combination of pseudorandom and deterministic test sets of the whole system, consisting of multiple cores, under given memory constraints, so that the total test time is minimized. Our approach employs a fast estimation methodology in order to avoid exhaustive search and to speed-up the calculation process. Experimental results have shown the efficiency of the algorithm to find near optimal solutions. 1 This work has been supported by the Swedish Foundation for Strategic Research (SSF) under the Strategic Integrated Electronic Systems Research (STRINGENT) program, by the EC project EVIKINGS (IST-2001-37592) and by the Estonian Science Foundation Grants 4300 and 5649. 1. Introduction Testing of systems-on-chip (SoC) is a problematic and time consuming task, mainly due to their complexity and high integration density [1]. To test the individual cores of a SoC the test pattern source and sink have to be available together with an appropriate test access mechanism (TAM) [2]. Due to the rapid increase of chip speed and test data volume, the traditional Automatic Test Equipment (ATE) based solution is becoming increasingly expensive and inaccurate. Therefore, in order to apply at-speed tests and to keep the test costs under control, built-in self-test (BIST) solutions are becoming a mainstream technology for testing such complex systems. BIST for digital logic (logic BIST) uses mostly pseudorandom tests. Due to several reasons, like very long test sequences, and random pattern resistant faults, this approach may not always be efficient. One solution to the problem is to complement pseudorandom test patterns with deterministic test patterns, applied from the on-chip memory or, in special situations, from the ATE. This approach is usually referred to as hybrid BIST [3]. One of the important parameters influencing the efficiency of a hybrid BIST approach is the ratio of pseudorandom and deterministic test patterns in the final test set. As the amount of resources on the chip is limited, the final test set has to be designed in such a way that the deterministic patterns fit into the on-chip memory. At the same time the testing time must be minimized in order to reduce testing cost and time-to-market.