IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 47, NO. 1, JANUARY 2000 141 Effects of the Inversion-Layer Centroid on the Performance of Double-Gate MOSFET’s Juan A. López-Villanueva, Member, IEEE, Pedro Cartujo-Cassinello, Francisco Gámiz, Member, IEEE, Jesús Banqueri, Member, IEEE, and Alberto J. Palma Abstract—The role of the inversion-layer centroid in a double-gate metal-oxide-semiconductor field-effect-transistor (DGMOSFET) has been investigated. The expression obtained for the inversion charge is similar to that found in conventional MOSFET’s, with the inversion-charge centroid playing an iden- tical role. The quantitative value of this magnitude has been analyzed in volume-inversion transistors and compared with the value obtained in conventional MOSFETs. The minority-carrier distribution has been found to be even closer to the interfaces in volume-inversion transistors with very thin films, and therefore, some of the advantages assumed for these devices are ungrounded. Finally, the overall advantages and disadvantages of double-gate MOSFET’s over their conventional counterparts are discussed. Index Terms—Charge carrier density, inversion layers, MOSFET’s. I. INTRODUCTION D OUBLE-GATE MOSFET’s (DGMOSFET’s) [1], [2] and related structures, such as gate-all-around transistors (GAA) [3], have been proposed as a serious alternative to the state-of-the-art standard bulk MOSFET’s. Many of the performance improvements attributed to these devices [4], [5] have been well proven, such as those characteristics shared with fully-depleted silicon-on-insulator (SOI) transistors of any kind: high subthreshold slope, reduced junction capacitances, improved isolation, and radiation hardness. Furthermore, they offer their own advantages, as the possibility of obtaining an extremely short gate length due to the screening effect of the bottom gate [6]–[8], and an approximately double inversion-charge density, due to the two channels, which allows the transistor width to be reduced by half, thus increasing the integration level. The lower channel length can also provide transport advantages if it translates into noticeable velocity overshoot. Nevertheless, the electron confinement also causes some disadvantages: 1) the low thermal-conductivity of the silicon dioxide can produce selfheating along the channel, thus increasing phonon scattering [9]; 2) the parasitic series resistance increases; 3) the very confinement of the electrons in the spatial coor- dinate leads to a lower localization in momentum space and, therefore, increased phonon scattering [10]–[12]. Manuscript received November 2, 1998; revised June 1, 1999. This work was supported by the DGES of the Spanish Government under Project PB97-0815. The review of this paper was arranged by Editor D. P. Verrret. The authors are with the Departamento de Electrónica, Facultad de Ciencias, Universidad de Granada, 18071 Granada, Spain (e-mail: jalopez@goliat.ugr.es). Publisher Item Identifier S 0018-9383(00)00158-1. There are other assumed advantages that are not totally clear, or that at the least require further research. Among these features are some of those attributed to the volume-inversion regime that have been controversial in the past, with questions raised re- garding the differences and similitudes between DGMOSFET’s and conventional bulk MOSFET’s [4], [13], [14]. When the ac- tive silicon layer is thin enough, the electron concentration in the channel peaks in the middle, and is said to be far from the inter- faces, thus leading to reduced scattering due to charged centers in the oxide layers and in their interface with silicon, and less influence of surface roughness [4]. Moreover, as all the silicon layer is able to carry is current, the current capability of these de- vices is said to be greater than the current capability of standard bulk MOSFET’s of double width. In order to assess the true ad- vantages of DGMOSFET’s for the microelectronic technology of the near future, these features must be analyzed in detail by comparing the transistors with their conventional counterparts. To make a realistic comparison, however, transistors with equiv- alent performance must be chosen. To study the electric current in a field-effect-transistor, two magnitudes must be taken into account: 1) the charge density in the channel and 2) the carrier velocity along it. The purpose of this paper is to analyze the charge distribution in a symmetric DGMOSFET with an extremely thin silicon film and to compare it to a high-performance bulk MOSFET, so that we deal with the first magnitude. Nevertheless, as the charge-distribution shape has direct consequences on the second magnitude, as it affects the scattering rates, some consequences on carrier transport are discussed. II. THE INVERSION-LAYER CENTROID The inversion-layer centroid in standard bulk MOSFET’s is defined as the average penetration of the inversion-charge dis- tribution into the silicon, and can be calculated as [15] (1) where is the electron concentration and is chosen at the back contact or at a point within the substrate neutral region, far enough from the oxide-silicon interface. Some of the authors have discussed the effects of this average penetration in standard MOSFET’s in detail [16]. However, in the case of a symmetric DGMOSFET (with the two gates of the same material and the 0018–9383/00$10.00 © 2000 IEEE