PVD TiN Hardmask for Copper Metallization ISSM Paper: PE-O-203 Zhigang Xie, Ashish Bodke, Jianming Fu, Rahul Jauhari, Magdy Abdelrahman Applied Materials, Inc. 3050 Bowers Ave., P.O. Box 58039, M/S 1151, Santa Clara, CA 95054 Zhigang_Xie@amat.com, Ashish_Bodke@amat.com, Rahul_Jauhari@amat.com, Magdy_Abdelrahman@amat.com Advanced Process and Metrology Equipment Abstract – With shrinking geometries and adoption of lower k dielectrics and thinner barriers to minimize device RC delay, there is a need for advanced patterning schemes. Hardmask technology is on demand as the photoresist(PR) films used in semiconductor fabrication need to be thinner to etch sub-45nm devices. Hardmask films provide high etch selectivity to low-k dielectrics and photoresist, serve as an anti-reflective coating, allowing partial via etch approach and eliminating ULK damage caused by the resist ash strip process. We have optimized PVD TiN process through hardware, process modifications to meet all the requirements of hardmask technology. We also present preliminary etch rate data and via profiles demonstrating the benefits of TiN hardmask. Further work to characterize adhesion and electrical performance is underway. INTRODUCTION With shrinking line-width and spacing, it has become increasingly challenging to minimize RC delays and cross- talk in interconnects, requiring the use of ultra low k dielectric materials (k≤2.5). This usually introduces porous low k materials in copper interconnects, which is more susceptible to strip damage. Further, as semiconductor fabrication technology advances and feature sizes continue to shrink, photoresist thickness is going down rapidly [1]. According to Semiconductor Industry Association (SIA) roadmap, ~500nm photoresist was used for patterning 150nm features using 248nm lithography. To pattern 120nm features, photoresist thickness has to be reduced to ~300nm using 193nm lithography. For sub-100nm device sizes, <200nm of photoresist may be necessary. Although resist thickness has continued to go down, its resistance to etch remains the same. Typical etch selectivity of resist to ARC is ~1:1 which means that ~100nm of the resist will be consumed during ARC open, leaving very little resist to etch the underlying substrate. Due to these constraints, development of new integration schemes has become critical, especially at 45nm technology node and beyond. Hardmask scheme offers a great alternative in addressing those challenges associated with the adoption of porous low k materials [2,3]. TiN is an excellent candidate for this application because in addition to meet the etch requirements, TiN has low reflectivity so as to work as anti-reflective film. Film deposition via PVD is production proven [4] so that it offers low cost of ownership. TiN etch process has excellent selectivity to low k dielectric and photoresist, and is well characterized. Using TiN as a hardmask allows use of a partial via etch approach, eliminating the need for a relatively higher k etch-stop layer. Trench etch can be performed without a photoresist mask, so that the ULK damaging ash strip process is no longer needed. In addition, TiN hardmask etching has minimum faceting of the trench top corners, thereby protecting the CD space. Further, TiN metal hardmask enables good Line Edge Roughness (LER), minimizes striations, and prevents 193nm resist poisoning. In this paper, we summarize the development of PVD TiN as a hardmask for Cu dual damascene application. Important properties of TiN film to be acceptable as a hardmask includes excellent blanket film thickness uniformity, particle performance and low cost of operation. We have developed Ti and TiN films with excellent Rs uniformity as a wetting & ARC layer for Al metallization. However, to meet hardmask requirements, the thickness uniformity and particle performance needed to be further improved. We briefly review hardware & process modifications to improve the thickness uniformity and particle performance of TiN films for hardmask application. We also review etch rate data, and present preliminary 100nm via profiles using 193nm lithography with and without TiN hardmask. EXPERIMENT RESULTS TiN films are deposited on an industry standard PVD platform. OmniMap tool was used to measure Rs, Rudolph Metapulse was used to measure thickness. Particles were measured at 0.2µm for in film and 0.16µm for mechanical. Low k dielectric (BDII) was deposited with PECVD, followed by UV curing. Etch was then subsequently performed to characterize the etch with and without hardmask. 5,000 wafers extended run was also carried out to check the performance modified process and hardware. Thickness Uniformity Optimization Although surface reflectivity changes with TiN thickness, the value will be stable to 60% relative to bare Si for a 40nm film, at a lithography wavelength of 248nm. Therefore, we optimize TiN thickness uniformity (1 sigma) with this standard anti-reflection- layer thickness (40nm). The current hardware can achieve <2% Rs uniformity but >5% thickness uniformity. To improve thickness uniformity, a new magnetron was designed so that a more uniform target erosion profile was demonstrated comparing to that with the current magnet (Figure 1). 1-4244-1142-4/07/$25.00 ©2007 IEEE