1166 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 56, NO. 6, JUNE 2009 Circuit-Level Impact of a-Si:H Thin-Film-Transistor Degradation Effects David R. Allee, Senior Member, IEEE, Lawrence T. Clark, Senior Member, IEEE, Bryan D. Vogt, Rahul Shringarpure, Sameer M. Venugopal, Shrinivas Gopalan Uppili, Korhan Kaftanoglu, Hemanth Shivalingaiah, Zi P. Li, J. J. Ravindra Fernando, Edward J. Bawolek, Senior Member, IEEE, and Shawn M. O’Rourke (Invited Paper) Abstract—This paper reviews amorphous silicon thin-film- transistor (TFT) degradation with electrical stress, examining the implications for various types of circuitry. Experimental mea- surements on active-matrix backplanes, integrated a-Si:H column drivers, and a-Si:H digital circuitry are performed. Circuit mod- eling that enables the prediction of complex-circuit degradation is described. The similarity of degradation in amorphous silicon to negative bias temperature instability in crystalline PMOS FETs is discussed as well as approaches in reducing the TFT degradation effects. Experimental electrical-stress-induced degradation results in controlled humidity environments are also presented. Index Terms—Amorphous silicon, flexible electronics, thin-film transistors (TFTs), threshold-voltage shift. I. INTRODUCTION A MORPHOUS silicon (a-Si:H) thin-film transistors (TFTs) are widely used in active-matrix backplanes for LCD displays on glass. There is significant interest in extending this technology to flexible substrates [1]–[5] for lightweight rugged conformal displays. Eventually, wearable flexible displays will be useful in applications such as providing real-time situational awareness for soldiers, police, firefighters, and other emergency personnel. The development of fully flexible digital electronic systems based on the a-Si:H TFT enabling applications beyond display pixels has already begun with the integration of display row and column drivers [6]–[8]. These drivers are normally implemented with external ICs. Integration in a-Si:H on the display backplane reduces interconnection count, reducing cost, and improving reliability. Manuscript received July 29, 2008; revised February 3, 2009. Current ver- sion published May 20, 2009. This work was supported by the Army Research Laboratory (ARL) under Cooperative Agreement W911NG-04-2-0005. The review of this paper was arranged by Editor J. Suehle. D. R. Allee, L. T. Clark, B. D. Vogt, R. Shringarpure, S. M. Venugopal, S. G. Uppili, K. Kaftanoglu, H. Shivalingaiah, Z P. Li, E. J. Bawolek, and S. M. O’Rourke are with the Flexible Display Center, Arizona State University, Tempe, AZ 85284 USA. J. J. R. Fernando was with the Flexible Display Center, Arizona State University, Tempe, AZ 85284 USA. He is now with the University of Notre Dame, Notre Dame, IN 46556 USA (e-mail: allee@asu.edu). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2009.2019387 Unfortunately, a-Si:H TFTs exhibit several undesirable elec- trical characteristics. They have carrier mobilities approxi- mately 1000× less than in single crystal silicon. Moreover, although P-type a-Si:H TFTs have been demonstrated, they have proven impractical due to even lower hole mobility. Amor- phous silicon TFTs are unstable and suffer from electric-field- induced threshold-voltage (V th ) shift [9]–[11]. This gradual increase in threshold voltage limits the lifetime of active-matrix backplanes and is exacerbated in low-temperature processes re- quired for flexible backplanes [1], [12]–[14]. Furthermore, V th is a strong function of duty cycle or “on” time. The increase in V th creates early wear out in general-purpose digital circuitry, where unlike the TFTs in a display backplane, the transistors operate continuously. The achievable lifetime determines the viable applications. Thus, circuit-design techniques are needed to slow or reverse the V th increase in a-Si:H TFTs for all circuit applications. In this paper, we review the a-Si:H TFT electrical per- formance in Section II. The degradation characteristics and mechanisms of a-Si:H TFTs are discussed in Section III. The degradation impact on several types of circuits is exam- ined, including display backplanes, display row and column drivers, and general-purpose digital circuitry, in Section IV. In Section V, similarities between the V th shift in a-Si:H TFTs and that in crystalline PMOS FETs due to negative bias temperature instability (NBTI) is presented along with experimental results of TFT degradation in the presence of controlled humidity. Section VI concludes this paper. II. AMORPHOUS SILICON TFTs The a-Si:H TFT developed at the Flexible Display Center is a bottom-gate inverted staggered structure (Fig. 1). A low- temperature (180 ◦ C) process on flexible substrates such as stainless steel and heat-stabilized polyethylene naphthalate is used. The gate metal is molybdenum patterned on the substrate and is beneath the a-Si:H active layer. The gate dielectric is silicon nitride. The nitride is passivated before the contacts are etched. Source/drain metal is sputtered on as an N+ amorphous silicon–aluminum bilayer. Metallization of indium–tin oxide and molybdenum is then applied. The circuits are annealed after fabrication at 180 ◦ C in nitrogen atmosphere for 3 h to simulate 0018-9383/$25.00 © 2009 IEEE