IEEE ELECTRON DEVICE LETTERS, VOL. 29, NO. 1, JANUARY 2008 93 Localization of Gate Bias Induced Threshold Voltage Degradation in a-Si:H TFTs Rahul Shringarpure, Student Member, IEEE, Sameer Venugopal, Student Member, IEEE, Lawrence T. Clark, Senior Member, IEEE, David R. Allee, Member, IEEE, and Edward Bawolek, Senior Member, IEEE Abstract—This letter describes a method to identify the channel region of hydrogenated amorphous silicon thin film transistors (a-Si:H TFTs) in which threshold voltage (V th ) degradation oc- curs. The TFTs are subjected to gate bias stress under different operating conditions. Asymmetry in the measured TFT drain current in the forward direction (same source and drain during stress and measurement) and reverse direction (interchanging the source and drain terminals) shows localization of the gate-voltage dependent V th shift mechanism. Based on the observations, a charge-based expression for V th shift is derived. Index Terms—Amorphous silicon thin film transistors (a-Si:H TFTs), circuit simulation, display technology, spice, threshold voltage degradation. I. I NTRODUCTION A MORPHOUS silicon thin film transistors (a-Si:H TFTs) suffer from prolonged gate bias stress V th shift (ΔV th ). In general, two mechanisms are considered responsible for V th instability in a-Si:H TFTs [1]: First, charge injection into the gate dielectric increases the fixed charge in the silicon nitride (a-SiN x ) layer. Second, dangling bond defect states are created in the a-Si:H channel region. The defect states in a-Si:H TFTs are located within the gate insulator (a-SiN x layer), at the silicon/insulator interface or within the aSi:H conducting channel [2], [3]. Generally, when modeling ΔV th , these are lumped together and the net V th shift is ex- pressed as ΔV th = ΔV e th - ΔV h th 2 = q · ΔN D C ox . (1) Here, ΔN D is the density of created defect states, ΔV e th is the threshold voltage shift from electrons, ΔV h th is the thresh- old voltage shift from holes, C ox is the gate capacitance and q is the electronic charge. This letter describes the experiment Manuscript received August 28, 2007; revised October 23, 2007. The review of this letter was arranged by Editor J. Sin. R. Shringarpure, L. T. Clark, and D. R. Allee are with the Electrical Engineering Department, Arizona State University, Tempe, AZ 85287-5706 USA (e-mail: rahul.shringarpure@asu.edu; Lawrence.Clark@asu.edu; David. Allee@asu.edu). S. Venugopal and E. Bawolek are with the Flexible Display Center, ASU Research Park, Tempe, AZ 85284 USA (e-mail: Sameer.Venugopal@asu.edu; Edward.Bawolek@asu.edu). Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LED.2007.911609 Fig. 1. Schematic representation of the stress conditions and degradation localization. N it is the density of interface defect states (dots) formation is limited to the extent of current flow (solid line) at the surface (a) and (b). (a) Linear mode stress affects channel length L. (b) Saturation mode stress extent limited to L - ΔL. with which the threshold voltage shift ΔV th is shown to be constrained to the a-Si:H to SiN x gate dielectric interface and to vary with bias conditions during both stress and measurement. The a-Si:H TFTs are subjected to varying gate bias stress and the current–voltage characteristics are measured under different operating conditions, e.g., in linear and saturation. Specifically, by controlling the transistor operating region, e.g., linear or saturation, and interchanging the source and drain after stress, a different apparent ΔV th is measured. II. EXPERIMENT It is well known in bulk-silicon MOSFETs that hot-electron degradation occurs only at the drain where hot electrons are injected [4], [5] When bulk MOSFETs are biased with the same drain and source (the “forward” configuration) as dur- ing hot-electron stress, the linear mode current is strongly affected, but I DSAT is not [6]. When the source and drain are reversed (“reverse” configuration) the MOSFET I DS is degraded for all V DS . Consequently, reversing the source and drain during measurement indicates the location of the hot-e degradation mechanism—as carriers are forced away from the Si-SiO 2 interface in saturation, the trapped oxide charge at the drain has no effect. At the MOSFET source the impact is maximized. Here, the same experiment is applied to a-Si:H TFTs to determine if the gate voltage induced ΔV th mechanism is similarly localized in the channel. The concept behind this experiment is illustrated in Fig. 1, with the interface defects 0741-3106/$25.00 © 2008 IEEE