IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 3, NO. 2, JUNE 2004 225 Transfer of Single Crystalline Silicon Nanolayer Onto Alien Substrate Alexander Y. Usenko, Member, IEEE, William N. Carr, and Bo Chen Abstract—Starting from the 60-nm node, future generations of mainstream semiconductor devices (i.e., CMOS) will be mostly manufactured from silicon-on-insulator (SOI) initial substrates with the top silicon layer having a thickness 50 nm or less. We describe a process that is capable for transfer of nanoscale thick layers. The layer is delaminated from a single crystalline silicon substrate and laminated onto another substrate, thus resulting in SOI. The process includes: 1) forming a trap layer for hydrogen in an initial substrate; 2) delivery of hydrogen to the traps by diffusion of monatomic hydrogen; 3) evolving the trapped hydrogen into a layer of hydrogen platelets; 4) stiffening of the surface of the initial substrate by laminating to another substrate; and 5) delaminating a layer from the initial substrate along the hydrogen platelet layer. Details of the new layer transfer process are described. A depth where the buried trap layer locates is critical for the process. An implantation of heavy ions is used to form the trap layer. A trap capacity for hydrogen is evaluated as a function of implantation conditions. Plasma hydrogenation is used to deliver atomic hydrogen to the traps. Electron cyclotron resonance, microwave, RF, and dc plasma are compared as the hydrogenation sources. Dependence of a thickness of a transferred layer as a function of the mass of implanted ions and implantation energy is described. Types of layer transfer faults are also de- scribed. Mechanisms of the layer transfer faults are suggested. We discuss limits of scaling down of the thickness of the layer that is transferred from one substrate to another. The scaling limit of our process is compared to the limits of other (SIMOX, Smart-Cut, and ELTRAN) processes. Index Terms—Hydrogen, implantation, plasma, platelets, silicon, silicon-on-insulator (SOI). I. INTRODUCTION S MART-CUT is a process [1] that allows manufacturing sil- icon-on-insulator (SOI) high-quality wafers in big quanti- ties that was not possible before with preceding SOI processes as SIMOX. However, Smart-Cut is still expensive because it re- quires hydrogen implantation in a high dose 5 10 cm [1]. Moreover, the dose should be implanted at a very low ion beam current (less than 80 mA [2], less than 4 1013 ions/cm /s [3], less than 0.1 mA [4], [5]). Many attempts are known to re- duce the dose and/or increase the dose rate. Most of the attempts Manuscript received August 19, 2003; revised December 29, 2003. This work was supported in part by the National Science Foundation under Small Business Innovation Research Award DMI-0216676. This paper was presented in part at the Symposium of Microtechnologies for the New Millennium 2003, Nanotech- nology Conference, February 23–27, 2003. A. Y. Usenko is with Silicon Wafer Technologies Inc., Newark, NJ 07102 USA (e-mail: usenko@si-sandwich.com). W. N. Carr is with the Department of Physics, New Jersey Institute of Tech- nology, Newark, NJ 07102 USA (e-mail: carr@njit.edu). B. Chen was with the Department of Physics, New Jersey Institute of Tech- nology, Newark, NJ 07102 USA. He is now with Silicon Wafer Technologies Inc., Newark, NJ 07102 USA. Digital Object Identifier 10.1109/TNANO.2004.828519 TABLE I SUMMARY OF PROCESSING CONDITIONS use double-specie implantation, such as helium-then-hydrogen [6]–[8], proving that the total dose required can be reduced to 2 10 cm in the best case. It has been suggested by Usenko and Carr [9] and Usenko [15] to reduce the total cost of the layer transfer process by diffusing hydrogen to a buried trap layer in silicon. Here, we are continuing that approach while using plasma for the hydrogenation. The International Technology Roadmap for Semiconductors 2001 [16] projects that the cap Si layer for SOI starting wafers will be 20–100 nm in thickness by 2004 to support processing of fully depleted CMOS circuits. Smart-Cut provide an inherent Si film thickness of approximately 500 nm and a minimum thick- ness of approximately 200 nm. 1 The thickness of the delami- nated layer in the Smart-Cut process depends on the energy of implantation of hydrogen. When the energy of the H implant is reduced below 20 keV to achieve thin delaminating, prob- lems arise [7]. Attempts have been reported to obtain a thin ( 200 nm) cap Si layer of SOI wafers. Qian et al. [7], and Qian and Terreault [17], [18] used low-energy hydrogen im- plantation (5–8 keV) in a regular Smart-Cut to get a thinner top SOI layer. They concluded that a kiloelectronvolt range hy- drogen implant is infeasible for layer transfer. Maleville et al. [19] reports 70-nm top Si SOI using touch polishing of an initial 500-nm layer. Srikrishnan [20] forms (by implantation) an etch stop layer inside of the transferred with Smart-Cut silicon film with a subsequent etching. Popov et al. [21] reports a layer-by- layer oxidation (of the film transferred with Smart-Cut) with subsequent stripping in diluted HF for thinning of the layer. All listed approaches increase SOI wafer production cost and de- grade thickness uniformity. Our study reports the plasma hy- 1 General specification for customized UNIBOND wafers, SOITEC, Bernin, France, 2002 1536-125X/04$20.00 © 2004 IEEE