Integrated Tool for Testing Timed Systems Hacène Fouchal 1 , Sébastien Gruson 2 , Ludovic Pierre 2 , Cyril Rabat 2 , and Antoine Rollet 2 1 GRIMAAG, Université des Antilles et de Guyane, F-97157 Pointe-à-Pitre, Guadeloupe, France Hacene.Fouchal@univ-ag.fr 2 CReSTIC/LICA, Université de Reims Champagne-Ardenne, BP 1039 F-51687 Reims Cedex, France {Cyril.Rabat,Antoine.Rollet}@univ-reims.fr Abstract. Some new protocols handle time constraints to model important as- pects (delays, timeouts, ..). This issue has to be taken into account in every step during its development life cycle, in particular in the testing step. This paper presents an integrated tool which permits to specify a timed system in various models (RT-LOTOS, IF, Timed automata) and then generates test sequences us- ing a new efficient algorithm. Illustrated examples show the differents steps of this new test generation method. Keywords: Protocol Engineering, Validation, Conformance Testing, Timed Au- tomata, Automata Theory. 1 Introduction In software development, conformance testing is highly needed in order to avoid catas- trophic errors and to tackle the industrial development of the product with confidence. Since a couple of years, time is considered as a crucial feature of many sensitive sys- tems as multimedia protocols, embedded systems, air traffic systems. Then it should be seriously considered by designers and developers. In this paper, we present a tool which is able to accept three different (RT-LOTOS, IF, Timed automata) models to describe any system to test. RT-LOTOS [1] is an exten- sion to the ISO language LOTOS [2]. In this part we use the RTL tool to derive Input Output Timed Automata. IF [3] is an intermediate form which may come from SDL or any other formal technique. We developped a translater able to derive Input Output Timed Automata from IF specifications. We have also taken into account the possibility to handle Timed automata used in the Uppaal [4] tool. Then we apply a technique of test sequence generation on the derived Timed Input Output Automaton (TIOA). A Timed Input Output Automaton (defined as an automaton where each transition can bear either an input action or output action and sometimes timing constraints), widely used for the description of timed systems. Our work is deeply inspired by the protocol engineering area where researchers usually deal with two main validation techniques: – the verification approach, which handles the system specification and tries to prove its correctness (in this case the system is a white box). Usually, the user properties are expressed by another formalism as temporal logics and must be verified on the specification by using a model-checker for example, F.F. Ramos et al. (Eds.): ISSADS 2005, LNCS 3563, pp. 153–166, 2005. c  Springer-Verlag Berlin Heidelberg 2005