IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 12, DECEMBER 2002 2271 The Partial Silicon-on-Insulator Technology for RF Power LDMOSFET Devices and On-Chip Microinductors Changhong Ren, Jun Cai, Yung C. Liang, Senior Member, IEEE, Pick Hong Ong, N. Balasubramanian, and Johnny K. O. Sin, Senior Member, IEEE Abstract—A new partial silicon-on-insulator (SOI) formation technology and the associated RF LDMOSFET device structure on silicon bulk substrate are proposed in this paper. The same tech- nology can also be applied to enhance the quality factor of the inte- grated on-chip microinductors. The proposed technology is able to reduce both drain/substrate parasitics and leakage current for de- vices fabricated on bulk substrate. At the same time, the approach overcomes the thermal problem encountered by devices fabricated on full-SOI substrate. To demonstrate the technology, both par- tial-SOI LDMOSFET and microinductor devices were fabricated on bulk wafer with their RF performance verified by laboratory measurements. Index Terms—CMOS process, LDMOSFET, microinductor, partial SOI, RFIC, SOI. I. INTRODUCTION H IGH performance RF amplifiers with good power-added efficiency and low fabrication cost are much preferred for future cellular products [1], [2]. The lateral double-diffusion MOSFET (LDMOSFET) device fabricated on bulk silicon wafer has been a popular candidate in RF narrow-band power applications [3]–[5]. However, the high parasitic output capac- itance on bulk substrate largely degrades its RF performances resulting to lower efficiency and power gain [6]–[8]. Besides, the highly unstable parasitic makes the output impedance matching quite difficult. Hence, high-quality RF power amplifier fabricated on bulk substrate for system-on-a-chip (SOC) integration is a difficult task [10], although the process compatibility with other CMOS circuitries can be easily made. Attempts were made to minimize the parasitic capacitance, such as by fabricating devices on a lightly doped substrate, optimization in layout design, by using silicon-on-anything Manuscript received May 20, 2002; revised November 11, 2002. This work was supported by the Agency for Science, Technology and Research of Singa- pore under Grant A*STAR/43/11/4-5. The review of this paper was arranged by Editor J. N. Burghartz. C. Ren is with the Department of Electrical and Computer Engineering, Na- tional University of Singapore, Kent Ridge, Singapore 119 260, and also with the Institute of Microelectronics, Singapore, Singapore 117 684 J. Cai and N. Balasubramanian are with the Institute of Microelectronics, Sin- gapore, Singapore 117 684. Y. C. Liang and P. H. Ong are with the Department of Electrical and Computer Engineering, National University of Singapore, Kent Ridge, Singapore 119 260 (e-mail: chii@nus.edu.sg).. J. K. O. Sin is with the Department of EEE, Hong Kong University of Science and Technology, Hong Kong. Digital Object Identifier 10.1109/TED.2002.807459 (SOA) technology and on the full SOI substrate [9], [11], [12]. However, devices fabricated on lightly doped substrate will induce hyper-abrupt capacitance characteristics when the drain voltage changes. This leads to degradation on system stability. Optimization on layout has a limited reduction in interconnect capacitance between metal layers but not on the inherent junction parasitic. With the buried oxide layer, the SOI LDMOSFET device has a much lower parasitic output capacitance, making it a better candidate for high frequency application. But the shortcoming is on the channel hot-spot temperature which is much higher compared to the bulk coun- terpart, due to the low thermal conductivity of the underlying buried oxide layer [26], [27]. Furthermore, the oxide layer also blocks the p sinker conduction path between the top source layer and the substrate in making the p substrate the source contact. The sinker connection is useful to eliminate the source metal interconnects and bond wires in order to minimize the source lead inductance for better RF performance [14]. In this paper, a concise partial-SOI platform formation technology on bulk silicon wafer and the associated RF power LDMOSFET device are proposed and experimentally demon- strated. Based on the new technology, it presents a lower output capacitance, higher output power added efficiency and good harmonics suppression properties. Also, the high -factor (up to 15 at 3 GHz) fully integrated microinductor was fabricated based on the same technology to demonstrate the versatile nature on SOC applications. II. NEW STRUCTURE AND DEVICE ANALYSIS Structures of the proposed LDMOS and inductor devices on partial SOI platform are shown in Fig. 1 (right) and Fig. 2 (right). For a good visual comparison, the bulk counterparts are drawn next to the proposed structures. A thick but limited length of oxide underneath the drain region is grown to form the par- tial-SOI platform. For the LDMOSFET device, it can effectively reduce the drain/substrate capacitance and the leakage current. For the microinductor, it is to raise the quality factor for the sim- ilar reason of having lower substrate parasitics [17], [18]. Being different from the full-SOI structure, the channel, the source and the p sinker regions in the partial-SOI structure remain located on bulk silicon. This will ensure the source-substrate connec- tivity via the p sinker remain intact. Also, it eliminates the thermal hot-spot problem in full SOI structure [27]. 0018-9383/02$17.00 © 2002 IEEE