598 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 32, NO. 4, APRIL 1997 Substrate Coupling Evaluation in BiCMOS Technology Juan M. Casalta, Xavier Aragon` es, and Antonio Rubio Abstract—The magnitude of switching noise coupled through common substrate in BiCMOS technology is analyzed. Noise dependence on collector resistance and buried layer doping of the noisy bipolar junction transistor (BJT) is obtained by means of simulation. It is observed that trends are different depending on bipolar transistor biasing: in common-collector, a low collector resistance is desired, while in common-emitter biasing, large values of make the transistor less noisy. A test chip is fabricated in 3- m BiCMOS technology to measure the substrate coupling produced by different BiCMOS inverter gates. These experimental measurements show that noise increases with tran- sistor size and collector resistance. Dependence on distance and speed of signal are also obtained, together with the effect of a guard ring. Index Terms— Crosstalk minimization, noise in BiCMOS cir- cuits, substrate coupling. I. INTRODUCTION T HE continuous trend toward miniaturization of circuits and packages carries interaction and switching noise trouble. Transients produced in digital circuits, working at high clock speeds, provoke disturbances that may affect, through the common substrate, sensitive analog parts in mixed-signal circuits. These phenomena have been experienced and simu- lation results can be found in the literature. A first solution to the problem is the physical partitioning of functions, splitting analog and digital circuits and integrating them in hybrid packages or in multichip modules [1]. Design solutions include noise minimization with guard rings [2], [3], while the use of technologies like silicon-on-insulator (SOI) has also been considered [4]. After adopting these basic measures, other factors must be taken into account, like inductance of package leads [2]. Given that all the work published to the moment deals with CMOS circuitry, the aim of this work is the evaluation of coupling in BiCMOS technologies. BiCMOS technologies are faster than CMOS and provide lower power dissipation than bipolar, with only three or four additional masking levels compared to CMOS technologies. However, even this small increase in process complexity makes BiCMOS designs more expensive than their CMOS counterparts [5], [6]. It is worth knowing whether the noise coupling issue will be an advantage or a disadvantage of BiCMOS. Results have been obtained through simulation and measurements on a test circuit and are compared with coupling evaluated in CMOS technology. Manuscript received November 27, 1995; revised September 25, 1996. This work is supported by the Spanish Research Commission (CICYT), project TIC95-0469 and by the EU ESPRIT Basic Research in the framework of ARCHIMEDES Project. The authors are with the Departament d’Enginyeria Electr` onica, Universitat Polit` ecnica de Catalunya, 08034 Barcelona, Spain. Publisher Item Identifier S 0018-9200(97)02474-8. II. SUBSTRATE COUPLING IN CMOS TECHNOLOGY Coupling in CMOS circuitry is produced when a switching MOS gate induces a substrate voltage disturbance that affects neighboring devices in two ways: first through capacitive coupling, by means of the depletion capacitances associated to source and drain regions, and second through body-effect coupling, as drain current depends on threshold voltage, which in turn is affected by nonzero source-bulk voltage. It can be demonstrated both analytically and by device simulation that the body-effect coupling becomes less important relative to depletion-capacitance coupling as the substrate doping is increased. Crosstalk analysis made with CMOS devices show substrate type to be of major importance on coupling magnitude [2], [3]. Uniform, lightly-doped substrates present important noise peaks, and their magnitude decreases linearly with increasing distance between coupled devices. Heavily-doped substrates with an epitaxial p layer present peaks an order of magnitude smaller if the substrate is well biased (a grounded backplane). Due to the substrate structure, coupling becomes independent of device distance above a certain limit [2], when lateral effects disappear and current flow is produced through the low resistive heavily-doped part of the die. III. SUBSTRATE COUPLING IN BiCMOS TECHNOLOGY Once the characteristics of substrate noise in heavily-doped substrates have been determined, coupling in BiCMOS pro- cesses will be analyzed. The study will be restricted to coupling between a bipolar n-p-n transistor and an NMOS device. The study is done through transient analysis with the two-dimensional device simulator MEDICI [7]. This program allows device connection to lumped circuit elements, so it can be used for circuit analysis. A typical structure of two coupled transistors is defined for the simulations, using parameters of a BiCMOS 3- m MIETEC-ALCATEL technology (Fig. 1). It can be observed that the substrate is heavily-doped p-type, with a thin p epitaxial layer on the surface. An n-p-n transistor’s collector is made up of a deep lightly-doped n diffusion, and a conductive (3 /sq.) n buried layer and plug, so that the collector resistance is minimized. The bulk is biased through a backside contact, and its parasitics are modeled with a 10 nH inductance. Given that in this technology we integrate bipolar and field- effect transistors, it will be necessary to distinguish between bipolar or MOS device acting as a noise source. A. Common-Emitter Bipolar Transistor as a Noise Source We first analyze the interaction between a bipolar and a MOS transistor when the collector voltage switches from 0018–9200/97$10.00  1997 IEEE