Nuclear Instruments and Methods in Physics Research A 572 (2007) 353–354 A CMOS analog front-end for silicon pixel detectors for g imaging in medical application Valentino Orsolini Cencelli a,Ã , Francesco de Notaristefani a,b , Enrico D’Abramo a,b , Andrea Fabbri b , Luca Zerilli b a INFN Sezione di Roma III, Rome, Italy b Dipartimento di Ingegneria Elettronica, Universita’ di Roma Tre Available online 30 November 2006 Abstract In recent works we presented the g0, a chip expressely designed for g imaging in medical application. The chip was designed to be the anode of an Integrated Silicon Pixel Array (ISPA) tube. This chip consists of a matrix of 1024 pixels each 135u by 135u, each pixel comprises a CSA, designed to handle signals of few thousand electrons, a shaper, a discriminator and a 10 bit event buffer. The chip addresses many issues that are essential for the realization of cheap and fast detectors. Particularly it integrates a DAC controlled biasing network and an energy discrimination system. In this work, we present the test system and the first test results for the g0. r 2006 Elsevier B.V. All rights reserved. PACS: 29.40.Mc; 85.60.Ha; 87.58.Fg; 84.30.Àr Keywords: Biomedical imaging; g-ray detection; Nuclear electronics; Readout electronics; Solid scintillation detectors 1. Introduction In recent years, we have presented an Application Specific Integrated Circuit (ASIC) for g imaging in medical application [1,2]. The chip is intended to be used as an Anode in an ISPA [3,4] tube, bump bonded [5] to a silicon matrix PIN detector. The chip presented in this paper is the second version of the chip in Refs. [1,2], where the design was integrated by a more powerful, test system. The chip consists, as the former, of an array of 32 Â 32 pixel cells, 135 Â 135 mm each. Single cells are equipped with a front- end preamplifier, pulse shaper and discriminator with locally programmable threshold. A leakage current compensation scheme and five bits configuration register are also integrated: three bits for local adjustment of the pixel discriminator threshold, one bit to switch between the test mode (where a test pulse is given to the front end connecting it to a capacitor and a step generator) and one bit that switches between two lines of global current summation, one for direct output to one of the chip pins and one that is connected to three comparators for trigger generation. A dedicated on-chip discriminator, which compares the current collected by all the cells with an externally programmable threshold performs the trigger for array readout. The chip is designed using the UMC 0.25 mm Fig. 1. 2. ASIC and test system The ASIC was designed with some circuits to perform tests and to verify the correct behavior of the system. Particularly, we integrated on the system an analog multiplexer, addressable by the digital logic, to verify the values of the biasing voltages given to the circuit. The values for the measured voltages are plotted in Fig. 2. Five test pixels were put at the side of the main matrix. The shaper outputs of these pixels were connected to an instrumentation amplifier (with a gain of 5) in order to characterize the front end response to the test pulses, in Fig. 1, is reported the oscilloscope plot in response to a test pulse equivalent to 3700e À (the undershot that is seen in the figure is due to the fact that this pulse was obtained by the ARTICLE IN PRESS www.elsevier.com/locate/nima 0168-9002/$ - see front matter r 2006 Elsevier B.V. All rights reserved. doi:10.1016/j.nima.2006.10.377 Ã Corresponding author. Tel./fax: +390655177216. E-mail address: valentino.cencelli@ieee.org (V.O. Cencelli).