Defect Analysis in Power Mode Control Logic of Low-Power SRAMs L. B. Zordan 1 A. Bosio 1 L. Dilillo 1 P. Girard 1 A. Todri 1 A. Virazel 1 1 LIRMM - Université Montpellier II / CNRS France E-mail: <lastname>@lirmm.fr N. Badereddine 2 2 Intel Mobile Communications 2600, route des Crêtes – 06560 Sophia-Antipolis, France E-mail: nabil.badereddine@intel.com Abstract— Low-power SRAMs embed power gating mechanisms for reducing static power consumption. Power gating is applied in SRAMs using power switches for controlling the supply voltage applied to the various memory blocks (array, decoders, I/O logic, etc.). This paper provides a detailed analysis based on electrical simulations to describe the impacts of resistive-open defects on the power mode control logic, which generates control signals of power switches. Keywords-component; SRAM, low-power design, failure analysis, memory test, power switch, power mode control logic. I. INTRODUCTION With the growing demand of hand-held devices, power dissipation has emerged as a major design concern. Simultaneously, technology scaling is shrinking device features as well as lowering the supply and threshold voltages, which cause a significant increase of leakage currents. Within System- On-Chips (SOCs), embedded memories are the densest components [1], hence arising as the main contributor to the overall SOC static power consumption. Various techniques have been proposed to reduce the static power consumption of SRAMs. At architectural level, power gating provides several power modes for a given SRAM device by varying the supply voltage applied to the core-cells and peripheral circuitry. Power gating is generally implemented using power switches, which are controlled by a power mode control (PM control) logic. Fault-free behavior of power switches and PM control logic is crucial for ensuring accurate and reliable operation of SRAMs. In our previous work [2], we analyzed faulty scenarios that may cause low-power SRAM faulty behaviors. In this paper, we provide an in-depth analysis of the impacts of resistive-open defects occurring in the PM control logic. II. LOW-POWER SRAM ARCHITECTURE The SRAM used in this paper embeds power switch (PS) blocks connected to the core-cell array and the peripheral circuitry. Such PS blocks are implemented through a network of PMOS transistors structured in N segments [3]. Core-cell array PS segments have 4 transistors, whereas peripheral circuitry PS segments have two transistors. Signals connected to the gate of each PMOS in a segment are generated by the PM control logic, shown in Figure 1, according to the power mode selected through primary inputs           and             . Signals Ctrl_CC0 to Ctrl_CC1 control the transistors of the core-cell array PS segments, while Ctrl_PC0 and Ctrl_PC1 control the transistors of the peripheral circuitry PS segments. Three power modes can be distinguished as: (1) active mode, (2) deep-sleep mode, and (3) power-off mode. In active (ACT) mode, all PMOS transistors are activated. In this case, the whole memory is connected to the main supply rail V DD , which enables the SRAM to perform operations. In both deep-sleep (DS) and power-off (PO) modes, all PMOS transistors are deactivated, thus, the SRAM is no longer connected to the main supply rail. In DS mode, a voltage regulation system generates a fixed voltage level Vreg, lower than the nominal V DD , to be provided to the core-cell array. The lower voltage Vreg still ensures data retention. In PO mode, the power supply voltage of the whole memory is shut off such that core-cells are no longer able to retain data. III. SIMULATION RESULTS We characterized the SRAM behavior in presence of resistive-open defects affecting the PM control logic primary outputs, as shown in Figure 1. We observed that all injected defects induce a delay on the activation of the PMOS they affect during wake-up (WU) phase from DS or PO mode to ACT mode. Def1 to Def3 and Def5 cause rush-in currents during WU phase, whereas Def6 leads to malfunctioning of operations executed after WU. REFERENCES [1] ITRS, 2011 edition. [2] L. B. Zordan et al, “Failure Analyzis and Test Solutions for Low-Power SRAMs”, Proc. of IEEE ATS, 2011, pp. 459-460. [3] S. K. Goel et al., “Testing and Diagnosis of Power Switches in SOCs”, Proc. of ETS, 2006, pp. 145-150. Figure 1. Power Mode control logic !"#! #%&’ ())) )*+,-./0 1.2& 345-,26*5 7)138 9%:;#;<=%>;"=9%;>?#!?@>#A"" B!"#! ()))