Built In Self Test (BIST) Survey - An Industry Snapshot of HVM Component BIST usage at Board and System Test Zoe Conroy (iNEMI BIST Project Chair) Cisco Systems Inc. HuiLi Jun Balangue Agilent Technologies Singapore PteLtd 1 Yishun Avenue 7 Agilent Technologies Singapore PteLtd 1 Yishun Avenue 7 Singapore 768923 170 West Tasman Drive San Jose, CA 95134, USA zfconroy@cisco.com Singapore 768923 huUi@agilent.com jun _ balangue@agilent.com Abstract With board and component technology and integration rapidly increasing and becoming more complex, the testing of boards standalone and in a system is becoming more dificult, time consuming and costly. This paper addresses integrated circuit (lC) Built In Self Test (BIST) usage at the board and system test levels to provide increased test coverage, reduced test time and cost. This paper presents the results of an IC BIST usage survey developed by the Intenational Electronics Manufacturing Initiative (iNEMI). The survey was intended to gauge the current adoption rate of IC BIST for board and system test, identiy any impediments to widespread use, and select areas for uture research. 1. iNEMI BIST Project The 2009 iNEMI Roadmap gap analysis [2] detennined that one of the greatest risks to High Volume Manufacturing (HVM) board test was the continuous erosion of testpoint access due to increasing bus speeds, higher densities and shrinking form factors. Ultimately, the In-Circuit Tester (lCT) will not deliver the necessary defect coverage required, despite the complementary efforts of Boundary Scan [1]. Integrated Circuit (IC) BIST could be an altenate solution to ICT and provide the necessary defect coverage and diagnostics, independent of test point access. Running IC BIST at the board level, also gives added coverage and reduced test and debug time. Accordingly, the iNEMI BIST project [3] was launched to look at the feasability of running IC BIST at board and system test, how well existing standards support it and whether recommendations should be made for new standards. The irst phase of the iNEMI BIST project was to create and deploy a survey to the electronics industry to gauge the current use of IC BIST in HVM board and system level testing. The objective was to understand existing IC BIST availability, how much it is used at the board and system levels and the current challenges. The survey also covered whether the industry thinks there is a uture in running IC BIST at board and system test, and what would enable its wider adoption and ease of use. Follow on phases of the project are planned to address the issues identiied by the survey and promote the adoption of BIST at board and system test. 2. The iNEMI BIST Survey 2.1. Survey Objectives The objectives of the BIST survey were as follows: • Find out what types of component BIST are used and what is available to run at the board and system levels. • Detemine whether component BIST tests are proprietary to the company that designed them. • Understand how component BIST tests are accessed at the chip and board/system levels. • Gather feedback on how effective component BIST tests are at catching defects at the board level. • Find out how many component BIST tests are curently used in board and system level test and whether there are any roadblocks to their use at these test steps. • Obtain data on how much the industry is relying on BIST as a uture test technique and what coverage is expected. • Finally, gather data the extent on which current test standards are being used or will be used. 2.2. Survey Methodology The BIST survey was developed by the iNEMI BIST working group members and was sent out to several industry mailer lists rom December 2009 to January 2010. 2.2.1. Survey Recipients It was determined that the survey should focus on two primary job unction areas. The irst group's job unction was the 'End Users' (EU) of BIST, which includes application development engineers for system-level BIST. The second group's job unction was that of Integrated Circuit (IC) BIST provider and BIST test development. Each group brings it own unique perspective to designing and implementing component BIST. The 'End Users' of BIST included the following unctions: • Printed Circuit Board (PCB) circuit designer, layout and routing engineers. • PCB Design for Testability (DFT) engineer doing PCB design to manufacturing testability. • PCB Test Engineer responsible for the design, implementation and maintenance of tests used in the manufacturing process for PCBs. • System Architect who deines the basic structure and core design features of a system. • System-level Application Engineer, who deines, evaluates and integrates system-level concepts. • Manufacturing Test Engineer who writes board/system manufacturing tests and runs production testing. • Field Service Engineer who installs, repairs and performs preventative maintenance at customer sites. • Service and Support Engineer at a service center or repair depot. 34 th Intenational Electronic Manufacturing Technology Conference, 2010