958 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 5, MAY 2013 Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation Aida Todri, Member, IEEE, Alberto Bosio, Member, IEEE, Luigi Dilillo, Member, IEEE, Patrick Girard, Senior Member, IEEE, and Arnaud Virazel, Member, IEEE Abstract—Power supply noise and ground bounce can cause considerable path delay variations. Capturing the worst case power supply noise at a gate level is not a sufficient indicator for measuring the worst case path delay. Furthermore, path delay variations depend on multiple parameters such as input stimuli, cell placement, switching frequency, and available decoupling capacitors. All these variables obscure the rapport between supply noise and path delay and make the selection of stimuli for worst case path delay a difficult task during test pattern generation. In this paper, we utilize power supply noise and ground bounce distribution along with physical design data to generate test patterns for capturing worst case path delay. We propose accurate close-form mathematical models for capturing the effect of power supply noise and ground bounce on path delay. These models are based on modified nodal analysis formulation of power and ground networks, where current waveforms are obtained from levelized simulation and cell library characteriza- tion. The proposed test pattern generation flow is a simulated- annealing-based iterative process, which utilizes mathematical models for capturing the impact of supply noise on path delay for a given input pattern. We perform experiments on ITC’99 benchmarks and show that path delay variation can be consid- erable if test patterns are not properly selected. Index Terms—Automatic test pattern generation (ATPG), deep submicrometer, delay test, ground bounce, pattern selection, power supply noise, timing analysis. I. I NTRODUCTION T HE ONGOING miniaturization of circuits at the nanome- ter regime has introduced significant changes on the device’s parasitics and behavior. Circuit densities increase with each nanotechnology generation because of smaller devices and larger dies, and, consequently, current density and total current consumption increase accordingly. Simultaneously, circuits with high switching frequencies impose faster cur- rent transients on power and ground distribution networks. Transient currents increase exponentially with each technol- ogy node and cause significant deviations on the voltage distribution. Such deviations of the voltage levels from their nominal values are referred to as “power supply noise and ground bounce.” Both these conditions are undesirable, as they Manuscript received September 6, 2011; revised January 19, 2012; accepted April 12, 2012. Date of publication June 6, 2012; date of current version April 22, 2013. The authors are with the Laboratoire d’Informatique de Robotique et de Microélectronique de Montpellier (LIRMM UMR 5506), Montpellier 34095, France (e-mail: todri@lirmm.fr; bosio@lirmm.fr; dilillo@lirmm.fr; girard@lirmm.fr; virazel@lirmm.fr). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TVLSI.2012.2197427 significantly impact signal propagation. Analysis shows that power supply noise and ground bounce can considerably affect circuit’s performance [1]. Furthermore, simulations show that delay can have a speed-up/slow-down effect depending on the noise conditions on the neighboring gates and/or the crosstalk between gates as shown, respectively, by [2] and [3]. We consider the uncorrelated behavior of power supply noise and ground bounce (independent noise peaks and frequencies) in order to represent them as realistically as they would occur in an actual design. Gates can be placed in different locations on chip and they do not experience the same power or ground noise due to temporal and spatial switching. Also, power and ground parasitics for each cell can vary because of their proximity to the nearest power and ground pins. Moreover, as all gates share the same power and ground network, there is also noise transfer that occurs from one region to its neighboring regions, which can cause further delay variations. Another important factor that leads to uncorrelated noise is the amount of decoupling capacitance available at a given region. In general, decoupling capacitors are not evenly distributed, resulting in different amounts of generated noise. Owing to the aforementioned reasons, we treat power supply noise and ground bounce as uncorrelated. Traditionally, the impact of power supply noise on delay was considered at the cell library development step where each cell was characterized for the worst case voltage drop. Such approach assumes that all cells experience the worst case voltage drop, which is unrealistic. Several other approaches have been proposed in the literature which can be grouped into two main areas: 1) power supply noise aware timing analysis methods and 2) power supply noise aware test pattern generation. In the first group, there has been a substantial amount of work on how to estimate power supply noise- induced worst case delay, notably [4]–[9]. In [4], the authors propose a method to compute the upper bound of circuit delay under voltage variations. A vectorless approach is presented in [5] to estimate the maximum delay under power supply noise, and a delay maximization problem is formulated as an optimization problem. Similarly, the authors in [6]–[9] provide a worst case delay analysis taking into account power supply variations. In the second group of works, such as [10]–[14], the authors propose different techniques for test pattern generation while considering the impact of power supply noise. These works target critical path delay maximiza- tion under power supply noise while maximizing switching activity using approaches based either on the Monte Carlo 1063-8210/$31.00 © 2012 IEEE