IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 3, MARCH 2011 457 Reliability Analysis and Optimization of Power-Gated ICs Aida Todri, Student Member, IEEE, and Malgorzata Marek-Sadowska, Fellow, IEEE Abstract—Power gating is an efficient technique for reducing the leakage power of electronic devices by disconnecting the power supply from blocks idle for long periods of time. Disconnecting gated blocks causes changes in the current densities of the grid branches and vias. For some gating configurations, dc current den- sities may increase in some grid locations to the extent that they violate electromigration (EM) constraints. In this paper, we ana- lyze the EM and infrared (IR) voltage drop effects in gated global power grids. Based on our analyses, we develop a global grid sizing algorithm to satisfy the reliability constraints on grid branches and vias for all feasible gating configurations. Our experimental results indicate that a grid initially sized for all blocks connected to it may be modified to fulfill EM and IR constraints for multiple gating schedules with only a small area increase. Index Terms—Electromigration (EM), power gating, power grid optimization, power noise, vias. I. INTRODUCTION P OWER distribution networks in high performance digital ICs are commonly structured as multilayer grids, as de- picted in Fig. 1. The global power grid network is typically de- signed in the early stages of the design process, when little is known about the power demands at specific chip locations. Cor- recting or redesigning the power grid in the later stages in order to improve its electrical characteristics can be prohibitively ex- pensive. On the other hand, over designing the power grid may lead to increased power consumption. With technology scaling, more transistors are packed on a chip and, at the same time, sub- threshold and gate leakage currents are increasing. These major factors increase the criticality of power management and affect the grid design such that: 1) over designing the grid is not an op- tion due to tight power budgets and 2) idle portions of the chip could be temporarily disconnected from the grid. Power gating is a technique that allows idle blocks to be disconnected from the power grid in order to reduce leakage current. Sleep transistors placed between the global and block level power grids enable the blocks to be turned on and off as needed. Such an implementation requires a multi- process with low- transistors used by the circuits and high- sleep transistors. Power gating saves power when idle blocks with Manuscript received April 16, 2009; revised July 20, 2009. First published December 18, 2009; current version published February 24, 2011. This work was supported by SRC Grant 1421, a gift from Apache Design Automation, and an Intel Corporation equipment grant. A. Todri is with the Computing Division, Fermi National Accelerator Labo- ratory, Batavia, IL 60510 USA (e-mail: atodri@fnal.gov). M. Marek-Sadowska is with the Electrical and Computer Engineering Department, University of California, Santa Barbara, CA 93106 USA (e-mail: mms@ece.ucsb.edu). Digital Object Identifier 10.1109/TVLSI.2009.2036267 Fig. 1. Power network with power gating. substantial leakage currents are disconnected from the global grid for sufficiently long periods of time. Disconnecting gated blocks causes large changes in currents flowing through the global grid’s branches and vias. A power-gated device may have several power gating con- figurations (PGCs). For example, the chip shown in Fig. 1 has two gating configurations: 1) only block is gated and 2) both blocks and are gated. In this work, we focus on the power and signal integrity of the global power grid in dc conditions. We model circuit blocks as current sources and the global grid as a resistive network. Induc- tive effects are ignored because we are performing dc analysis. We only consider the working and/or sleep mode of gateable blocks rather than their transition modes. Thus, we ignore the power up/down currents when power gating is activated/deacti- vated. This is because our goal is to capture the static average current flows that last for considerable amounts of time and can lead to potential electromigration (EM) problems during the chip’s operational lifetime. We analyze currents flowing in the global grid branches and vias and show that a global grid opti- mized for all blocks connected to it may be violating EM con- straints for certain PGCs. This observation is counterintuitive, as turning off a block reduces the amount of current flowing on the global grid; but, locally, current may be crowded in some branches or vias, which can lead to EM violations. As vias have cross-sections smaller than the grid branches, they can fail sooner than the grid branches [1], [2] due to EM caused by large current densities. The existing literature on grid sizing for dc conditions de- scribes techniques to optimize the grid area under voltage drop [infrared (IR)] and EM constraints for one configuration of all circuit blocks connected to the grid [3]–[7]. These methods cannot be directly applied to optimize the power-gated grids 1063-8210/$26.00 © 2009 IEEE