A Copper CMOS-MEMS Z-axis Gyroscope Hao Luo * , Xu Zhu * , Hasnain Lakdawala * , L. Richard Carley * and Gary K. Fedder *† * Department of Electrical and Computer Engineering and † The Robotics Institute Carnegie Mellon University, Pittsburgh, PA 15213-3890 ABSTRACT This paper reports the first thin film Z-axis gyroscope fabricated in a copper CMOS-MEMS process [5]. It works in the ambient pressure of 1atm and does not depend on Q enhancement. The sensor is integrated with the conditioning circuits in a commercial low-k digital copper CMOS pro- cess. The benefit of the copper CMOS-MEMS process includes high mass density and low stress. The device was fabricated in the UMC 0.18 μm six copper layer CMOS process with a dimension of 410 μm by 330 μm. It consists of an outer rigid vibrating frame and an inner accelerometer to detect the Coriolis force. Measured driving mode reso- nant frequency is 8.8 kHz, the sensitivity is 0.8 μV/°/sec and the noise floor is 0.5 °/sec/ . INTRODUCTIONM Many micromachined capacitive gyroscopes have been reported [1][2][3][4], where many of them require either vacuum packaging or multi-chip assembly. An inte- grated gyroscope has possible advantages such as lower cost and higher sensitivity due to less parasitic capacitance. Post CMOS micromachining [5] enables the integration of circuits and mechanical sensors on a single chip. A CMOS- MEMS Z-axis gyroscope fabricated in this process with a conventional aluminum CMOS chip has been reported in [6]. The drawback of the Al version is that the device suf- fers severe out-of-plane curl because of large stress in the multi-layer structure. Potential improvement methods include using low stress material and thicker layers, which led to the investigation of using a six-layer Cu CMOS pro- cess. COPPER CMOS MICROMACHING PROCESS The gyroscope described in this paper combines high- aspect-ratio CMOS micromachining technology [5] and the copper CMOS technology. It is fabricated in the UMC 0.18 μm six copper layer low-k CMOS digital process. The reason to choose the copper process includes a) the copper layer is plated at low temperature and it has lower stress, b) six combined copper and dielectric layers provide thick structures (8 μm Cu vs. 5 μm Al). Compared to three layers in the aluminum version, the CMP copper process is more uniform and is expected to have less curl. Other benefits from the copper process include higher mass density (8.96 g/cm 3 Cu vs. 2.7 g/cm 3 Al) and low-k oxide. The mass is critical for inertial sensing as it directly limits the acceleration noise floor. The low-k process results in lower parasitic capacitance and thus has higher sensitivity when on-chip capacitance sensing technology is employed. The layout of circuits with micro-structure patterning in the metal layers is sent out for copper chip fabrication. Figure 1(a) shows the cross section of the chip after copper CMOS fabrication. After the foundry fabrication, two dry etch steps, similar to the aluminum CMOS-MEMS process [5], are used to define and release the mechanical structure. In the first step of post CMOS processing (Figure 1(b)), Hz Figure 1: Copper CMOS-MEMS process. (a) CMOS chip after fabrication (b) anisotropic RIE removes dielectric (c) isotropic RIE undercuts silicon substrate 0.18μm n-well CMOS gate polysilicon low-k glass silicon substrate top copper sixth copper layer layer top copper mask released microstructure stator exposed silicon (a) (b) (c) 0-7803-7185-2/02/$10.00 ©2002 IEEE 631