IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 8, AUGUST 2006 1757 A 5-GHz 20-dBm Power Ampliﬁer With Digitally Assisted AM-PM Correction in a 90-nm CMOS Process Yorgos Palaskas, Member, IEEE, Stewart S. Taylor, Stefano Pellerano, Member, IEEE, Ian Rippke, Member, IEEE, Ralph Bishop, Ashoke Ravi, Student Member, IEEE, Hasnain Lakdawala, Member, IEEE, and K. Soumyanath, Member, IEEE Abstract—This paper presents an integrated CMOS power ampliﬁer and a technique for correcting AM-PM distortion in power ampliﬁers. The linearization technique uses a varactor as part of a tuned circuit to introduce a phase shift that counteracts the AM-PM distortion of the power ampliﬁer. The varactor is controlled by the amplitude of the IQ baseband data in a feedfor- ward fashion. The technique has been demonstrated in a 5-GHz class-AB CMOS power ampliﬁer designed for WLAN applications and implemented in a 90-nm CMOS process. The power ampliﬁer delivers 16 dBm of average power while transmitting at 54 Mb/s (64 QAM). The proposed linearization technique is shown to improve the efﬁciency of the power ampliﬁer by a factor of 2.8. Index Terms—AM-PM distortion, linearization, power ampliﬁer (PA). I. INTRODUCTION T HE power ampliﬁer (PA) is one of the remaining bottle- necks in the full integration of wireless transceivers, es- pecially in pure CMOS processes. For example, most commer- cial solutions for 802.11a WLAN use an external PA to drive the antenna. This is because integrated power ampliﬁers tend to disturb sensitive analog signals on the same die (e.g., VCO pulling), and they usually achieve inferior performance com- pared to external PAs implemented in InGaP and SiGe technolo- gies. A number of solutions exist for dealing with the coupling is- sues (see Section II). Also, a number of linearization techniques have been proposed to improve the performance of integrated CMOS PAs. For example, [1] proposes a technique where the nonlinearity of a class-AB nMOS-based PA is counteracted by an inverse nonlinearity introduced by a pMOS transistor in par- allel. Reference [2] proposes a negative feedback technique for eliminating AM-PM distortion. Publications also continue to appear on more traditional linearization techniques, e.g., carte- sian feedback [3], dynamic biasing, digital predistortion [4], [5], etc. All these techniques present implementation difﬁculties that have prevented their widespread adoption. The technique of [1] Manuscript received December 10, 2005; revised March 22, 2006. Y. Palaskas, S. S. Taylor, S. Pellerano, R. Bishop, A. Ravi, H. Lakdawala, and K. Soumyanath are with the Communications Circuits Laboratory, Intel Corpo- ration, Hillsboro, OR 97124 USA (e-mail: palaskas@ieee.org). I. Rippke was with Intel Corporation, Hillsboro, OR 97124 USA. He is now with Xpedion Design Systems, Inc., Macungie, PA 18062 USA. Digital Object Identiﬁer 10.1109/JSSC.2006.877255 Fig. 1. Simpliﬁed schematic of the power ampliﬁer. might reduce the gain of the power ampliﬁer. The feedback tech- niques of [2] and [3] can result in increased complexity and die area, increasing cost. Digital predistortion techniques [4], [5] might require an increase in the bandwidth of the baseband sig- nals, resulting in higher power dissipation in the digital base- band. This paper proposes a practical, low-cost PA linearization technique, and demonstrates its robustness through extensive measurements. The linearization technique and a ﬁrst integrated implementation of the power ampliﬁer were ﬁrst presented in [6]. Here we report on an improved version of the power am- pliﬁer along with a more in-depth treatment of the linearization technique. The paper is organized as follows. Section II presents the design of an integrated CMOS power ampliﬁer targeted for WLAN applications. Section III discusses a digitally assisted technique for reducing AM-PM distortion in power ampliﬁers. Section IV presents measurement results that demonstrate the functionality of the proposed linearization scheme. II. POWER AMPLIFIER DESIGN Fig. 1 shows a simpliﬁed schematic of the two-stage PA used in this work. The pseudo-differential nature of the design min- imizes coupling to sensitive nodes, e.g., the VCO. It also re- duces the effect of parasitic ground inductance since part of the output current circulates locally between the complementary output devices and does not have to ﬂow through the parasitic ground inductance. Thick gate devices with GHz were used to maximize the voltage swings and the efﬁciency of the PA by reducing the insertion loss of the output matching net- work. Cascode transistors improve the stability of the ampliﬁer. 0018-9200/$20.00 © 2006 IEEE