F-Scan Test Generation Model for Delay Fault Testing at RTL using Standard Full Scan ATPG Marie Engelene J. Obien, Satoshi Ohtake, and Hideo Fujiwara Graduate School of Information Science, Nara Institute of Science and Technology, Japan E-mail: {obien-j, ohtake, fujiwara}@is.naist.jp Abstract—In this paper, we propose a new test generation method for F-scan delay fault testing that uses standard full scan delay fault automatic test pattern generation (ATPG). This method shows that it is possible to generate test patterns fast for F-scannable register-transfer level circuits, which use available functional elements and paths for testing in creating F-scan-paths, by using currently available commercial ATPG tools for gate- level scan circuits. The method is based from the constrained ATPG technique for stuck-at-faults, thus only the applicable test vectors to the F-scan-paths are generated. This work achieves high fault coverage by using the F-scan hybrid approach for delay fault testing that combines both skewed-load and broadside test application strategies. Experimental results show the comparison of our proposed method with gate-level full scan. I. I NTRODUCTION To ensure high test quality of larger and more complicated chips, there is a growing emphasis on at-speed testing by the IC manufacturing industries. Since the trend is towards the miniaturization of geometric sizes of chips while increasing gate count, timing defects are becoming more of a concern [22]. These timing-based defects may still be left undetected despite achieving high test coverage for stuck-at faults. From an initialization point to an observation point, these defects are detected when the amount of time it takes for a desired transition exceeds the period allowed for it. Thus, at-speed testing is necessary. Scan-based delay testing is increasingly utilized as a cost effective alternative to the at-speed functional pattern approach to test large scale chips for performance-related failures due to its advantages: (1) high test coverage and (2) reasonable development effort [23], [4], [6]. However, an advantage of functional testing is yield unlike the standard scan-based approach, which results in overtesting. In scan-based delay tests, test patterns are generated by an automatic test pattern generation (ATPG) tool for circuits with full scan chains. Since full scan design allows any pattern to be generated for the circuit, some testable states may not even be functionally reachable. Thus, there is a need for a testing method that has the advantages of scan-based delay testing and has the capability to reduce overtesting. Moreover, the two techniques for scan-based delay testing have their disadvantages. In the skewed-load approach [7], there is a requirement to handle the strict clock timing. This is solved in the broad-side method [8], but the fault coverage is not as high as skewed-load approach. Therefore, there is also a need for a delay fault testing method that has high fault coverage and can easily handle the clock timing to enable scan in the circuit. In our previous work [2], [3], [20], we have proposed a new DFT technique that utilizes available functional nodes and paths in a register-transfer level (RTL) circuit for testing. The method called F-scan proved to be better than full scan in terms of area overhead, test application time, and reduction of overtesting. Since we employ constrained ATPG [20] accord- ing to the F-scan-paths used for testing, only valid patterns can be generated for F-scan. We also extended constrained ATPG into a hybrid model for F-scan delay fault ATPG that achieves high fault coverage in [21]. The test patterns can be automatically applied to F-scannable circuits at-speed because of the RTL DFT mechanism, hence, there are no difficulties for the scan-enable timing. Furthermore, since the hybrid model includes the constraints, generated test patterns are also functionally reachable states as much as possible. However, this method is incomplete because using the two-time frame model with constraints takes too much effort and time during test generation. In order for F-scan to be practically applicable to today’s circuits, there is a need for it to be integrated to the available technology. Hence, we complete the F-scan delay fault test generation model in this work. In this paper, we propose a novel scan-based delay fault test generation method applicable to F-scannable RTL circuits using the standard gate level full scan delay fault ATPG. Previously, we used a standard combinational stuck-at ATPG method for two-time frames, wherein a constant value for the fault is assigned in the first time frame and stuck-at-fault is tested in the second time frame. As the circuit grows larger, the difficulty of fault simulation in this manner becomes harder and longer to handle. This is because the current ATPG tools do not have any information as to how to handle F-scan-paths. Therefore, using the standard full scan delay fault ATPG, which the current ATPG tools are already equipped to handle, improves test generation by magnitudes of time. This work also shows how F-scan can be practically integrated to the current digital design flow. II. PRELIMINARIES Scan-based delay fault testing has been widely explored in literature [5]-[14]. These works are done with the use of full scan DFT. Thus, all flip-flops are converted to standard scan flip-flops to allow delay fault testing. In [12], [13] however, the 2011 IEEE European Test Symposium, May 2011. ス