2.1 zyxwvutsrq Mobility Enhancement in Strained Si NMOSFETs with Hf02 Gate Dielectrics zy K. Rim, E.P. Gusev, C. D’Emic, T. Kanarsky*, H. Chen*, J. Chu, J. Ott, K. Chan, D. Boyd*, V. Mazzeo*, B.H. Lee*. A. Mocuta*, J. Welser”, S.L. Cohen, zyxwv M. leong*, and H.-S. Wong IBM T. J. Watson Research Center, Yorktown Heights, NY; *IBM Microelectronics Division, Hopewell Junction, NY Phone: 9 14-945-2946 e-mail: zyxwvuts uitn@iis. zyxwvuts i/?m.com Abstract Integration of strained Si and high-K gate dielectric is demonstrated for the first time. While providing a zyxwvuts >IOOOx gate leakage reduction, strained Si NMOSFETs with HfOz gate dielectric exhibit 60% higher mobility than the unstrained Si device with HfOz gate dielectrics. and 30% higher mobility than the conventional Si NMOSFETs with SiOz gate dielectric (universal MOSFET mobility). Introduction Gate leakage reduction in ultra thin gate dielectric is the main motivation for the search of high-K materials [I, 21. Electrical results on various candidate materials such as HfO2 and A1203 have shown leakage reduction by orders of magnitude, but have also highlighted the integration challenges such as charge trapping- related VT instability and mobility degradation. On the other hand, dramatic mobility enhancements have been reported in strained Si MOSFETs [3-61. Biaxial tensile strain in Si splits the conduction band degeneracy. reducing the intervalley phonon scattering and increasing the electron mobility. In this report, we demonstrate that integration of high-K dielectrics with strained Si significantly enhances electron mobility. Furthermore, we use the analysis of the effective mobility characteristics to gain understanding of the mechanisms that limit mobility in the high-K dielectricisi interface. Fabrication and Electrical Characteristics Strained Si and HfO? gate dielectrics were integrated using a standard CMOS process modified for the material compatibility zyxwvuts [5]. Fig. 1 shows a schematic illustration of the device structure. A thin layer of tensile-strained Si was epitaxially grown on a -1.5 pm thick layer of relaxed SiGe (1 5% [Gel) by UHVCVD. Devices were also fabricated on the control CZ Si substrates for comparison. After the device isolation and well implants, a 3 nm-thick HfO? layer was deposited by ALD [I] on a thin (sub-I nm) interfacial oxynitride. The control devices were fabricated at the same time with a 2.2 nm- thick conventional nitrided SiOz on both CZ Si and strained Si substrates (Table I). After polysilicon gate deposition and patterning, the fabrication process continued with the spacer formation, sourceidrain implant, activation anneal, and silicidation. The XTEM micrograph of the gate stack is shown in Fig. 2. The split C-V technique was used to measure the gate to inversion channel capacitance as shown in Fig. 3. The inversion equivalent oxide thickness (EOT,,,,.) was 2.8 and 3.1 nm for HfOz and SOz, respectively. The zyxwvutsrqpon C-V’s in the HfO? devices exhibited shift in the positive gate bias direction due to the fixed and trapped charges, consistent with previous reports [I]. Gate leakage current is shown as a function of the gate bias in Fig. zyxwvuts 4. Although the T,,,,. is -0.3 nm thinner in the HfOz devices, a significant leakage reduction is observed due to the higher dielectric constant. Compared with SiOz at an equivalent zyxwvuts Ti,,, and gate over- drive, HfOz provides more than IOOOx reduction in gate leakage current (Fig. 5). Long channel NFET ID-VGs characteristics are shown in Fig. 6. The strained Si device with HfO? gate dielectric (“Hf02/SS”) exhibits an excellent subthreshold slope of -80 mVidec, comparable to the SiOz control devices. Near the threshold, the subthreshold slope is slightly degraded in the HfOz devices possibly due to the combination of charge trapping and lower mobility near and below the threshold. However, the comparison of ID- V, characteristics at equivalent gate over-drives (Fig. 7) show that the output current of the HfOziSS device slightly higher (comparable when T,,,,. difference 12 0-7803-7312-X/02/$17.00 02002 IEEE is accounted for) than the CZ Si device with Si02 (“Si02/CZ”) due to the higher mobility in the HfOz/SS device above the threshold. Effective electron mobility was extracted using I-V and C-V measurements on large area NFETs [7]. Inversion charge density Q),71. was calculated by integrating the gate-to-channel capacitance. and the vertical effective field E,.,, was calculated by [7]: NMOSFET Mobility Characteristics 1 Er ‘ QdPi + ’ e,,,. ‘” si 1 where a,,,, is the integrated maximum depletion charge. Fig. 8 shows the comparison of effcctive mobility. The inobility of the SiOz/CZ device closely follows the universal mobility [7] as expecled, and the high mobility in the strained Si device with Si02 (“SiO;!/SS”) is consistent with the reported enhancement of NFET mobility in strained Si NFETs [5]. The mobility of the CZ Si devicc with Hf02 (“HfOz/CZ”) is degraded compared to the universal mobility, consistent with the previously reported results ([I] for example). However, the mobility of the HfOziSS dcvicc is enhanced over the universal MOSFET mobility for Eel, of >I MVicm. At 1.4 MVicm, the HfOJSS device exhibits a 30% higher mobility than the universal mobility and the SiOziCZ control devicc, and a 60% higher mobility than the HfOz/CZ control device. This represents, to our best knowledge, the best mobility characteristics achieved in FETs with high-K dielectrics. The amount of strain-induced mobility enhancement in the HfO2 device is comparable to that observed in the Si02 devices. Strained Si devices with A1203 were also fabricated, and exhibited similar enhancements over the previously reported mobility of the A1203/CZ devices [I, 21. Analysis of HfO,-limited Mobility The mobility characteristics of the Hf02/SS devices suggest that the Coulomb scattering due to the trapped and fixed charges in the dielectric may be the dominating mechanism responsible for mobility degradation observed in the NFETs with high-K dielectrics, MOSFET mobility can be expressed as a Matthiessen’s sum of the mobilities limited by various mechanisms such as Coulomb, phonon, and surface roughness scattering (inset in Fig. 8) [7]: It has been experimentally shown that strain in Si enhances the electron mobility in the intermediate to high E<,,! range where the mobility is limited by phonon and surface roughness scattering [5]. The large mobility enhancement exhibited by the HfOz/SS device over the Hf02/CZ device strongly suggests the absence of another mobility-limiting scattering mechanism related to HfOz in such E, range. In other words, if there were a mechanism that limits the mobility at high effective fields (such as increased phonon or roughness scattering), one would not expect to see the dramatic. strain-induced mobility enhancement over the universal mobility. Fig. 9 shows the mobility component limited by the Hf02-related scattering mechanisms. These mobility components were computed for the CZ Si and SS devices by taking the difference of the measured mobility of the SiOz and HfOz devices (inset in Fig. 9). The Hf02-limited mobilities extracted from strained Si and CZ Si are comparable in magnitude within the accuracy of the analysis, and show a positive power dependence on carrier density, characteristic of Coulomb scattering-limited mobility that becomes less dominant with increasing amount of screening by free carriers. Integration of strained Si and high-K dielectrics provides an improved trade-off between device performance and gate leakage. l/pIold = l/pCo,d + I/pplronos + ‘/pwrf rotqh. 2002 Symposium On VLSl Technology Digest of Technical Papers