IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 21, NO. 3, MARCH 2002 291 An Analysis of System Level Power Management Algorithms and Their Effects on Latency Dinesh Ramanathan, Sandra Irani, and Rajesh K. Gupta Abstract—The problem of power management for an embedded system is to reduce system level power dissipation by shutting off parts of the system when they are not being used and turning them back on when requests have to be serviced. Algorithms for this problem are online in nature; the algorithm must operate only with access to data that it has seen so far and without access to the com- plete data set or its characteristics. In this paper, we present on- line algorithms to manage power for embedded systems and dis- cuss their effects on system latency. We introduce competitive analysis as a formal framework for the evaluation of various power management algorithms. Compet- itive analysis does not depend on the distribution of interarrival times of requests. In this context, we present a nonadaptive on- line algorithm, analyze its behavior, and show that it is optimal. In this paper, we also present a lower bound on the competitiveness of any adaptive algorithm. We show that no adaptive online algo- rithm can dissipate less than about 1.6 times the power dissipated by the optimal offline algorithm in the worst case. We also show that in order for any online algorithm to achieve this lower bound, it may have to maintain a complete history of the interarrival times of the requests in the input sequence. Since this is not practical, we present a simple algorithm that uses only the last interarrival time to predict the arrival of the next request. We show that this algo- rithm performs as well as previously proposed heuristics for the problem; however, we can bound its worst case performance. In all our formal analysis, we do not model the service time for a re- quest, i.e., we assume that requests are services instantaneously. To test the performance of all the proposed algorithms and com- pare their performance against previously propose heuristics, we use the disk drive of a laptop computer as an embedded system. In our experiments, we model service times, i.e., we assume that the time to service requests is proportional to the size of the request. Under these conditions, we observed that in some cases a simpler algorithm that shuts down the system whenever it encounters an idle period performs better than the proposed adaptive algorithms. Another contribution of this paper is an analytical explanation of this observation. The final contribution of this paper is the pre- sentatation of an analytical proof that upper bounds the latency incurred by a subsystem, which employs a shutdown power man- agement policy. This allows system designers to effectively tradeoff the savings in power with the increase in the system latency due to aggressive shutdown power management schemes. Index Terms—Competitive ratio, embedded systems, latency, online algorithms, power management algorithms, service times, system level power. Manuscript received September 4, 2000; revised September 10, 2001. This paper was recommended by Associate Editor M. Pedram. The work of S. Irani was supported in part by NSF under Grant CCR-9625844 and Grant CCR- 0105498 and in part by ONR under Award N00014-00-1-0617. The work of R. K. Gupta and D. Ramanathan was supported in part by NSF MIP, in part by ARPA/ITO PACC under Grant F33615-00-C-1632, and in part by SRC under Grant 2001-HJ-899. The authors are with the Department of Information and Computer Science, University of California, Irvine, CA 92697 USA (e-mail: dinesh@ics.uci.edu; irani@ics.uci.edu; rgupta@ics.uci.edu). Publisher Item Identifier S 0278-0070(02)01780-3. I. INTRODUCTION P OWER dissipation in a very large scale integration (VLSI) system is a primary design consideration. In the design of portable computing devices, greater attention has to be paid to power estimation and management techniques. Over the past few years, methods to estimate and minimize power in the de- sign of circuits have been reported. Several excellent reviews of power minimization techniques are presented by Pedram [9], Devadas and Malik [10], Chandrakasan and Brodersen [14], Najm [11] and Luca [26]. Low power VLSI design can be achieved at various levels of abstraction during the design process. These include the system level, behavioral level, the register transfer level (RTL), and the gate level. Most techniques in the literature are focused at minimizing power at the RTL level. This paper focuses on the problem at the system level. A. System Model Our model of the system is a reactive real-time embedded system that continually reacts to the stimuli coming from its environment and performs this interaction under timing con- straints. This interaction causes the system to dissipate power in order to service the request. The interarrival time between requests is typically unknown and may not fall into any pat- tern. The requests typically arrive unpredictably and generally do not fall into well-known probability distributions [1], [2], [4], [5]. Therefore, a good power management strategy would selec- tively turn on and turn off the system to minimize the overall power consumption based on the arrival of the requests. In par- ticular, the optimal power dissipation will be by an algorithm that knows the interarrival times between requests ahead of time. Further, during system level design, the internals of the system under consideration are not known. In order to determine an ef- fective power management strategy for such a system, we as- sume that at least one power metric of the system is known: the ratio of the idle and the startup power dissipation. In this paper, we discuss strategies that selectively shutdown subsystems and turn them back on when needed. One side effect of shutting down subsystems and restarting them when required is an increase in the subsystems’ latency. When a subsystem is shut down and needs to be restarted, it incurs some delay overhead before the subsystem is initialized and is ready to service input requests. Since power management is needed for subsystems that are timing critical, the effect of latency arising from the power management scheme is crucial to the design of a system that complies with its timing require- ments. This paper analyzes the effects of power management on the latency of the system. The tradeoff between latency and 0278-0070/02$17.00 © 2002 IEEE