IEEE TRANSACTIONS ON COMPONENTS, HYBRIDS, AND MANUFACTURING TECHNOLOGY, zyxwvutsrq VOL. 15, NO. 5, OCTOBER 1992 zyxwv 615 DeveloDment and Analvsis of an Automated Test System for the Thermal Characterization of IC Packaging Technologies Sean Cian Abstract-This paper will report on the development of an automated test system for the thermal characterization of IC packages. A range of thermal test chips which have also been developed will be described. The thermal test system is discussed in detail in terms of the temperature sensor calibration algorithm and the error budget associated with junction-to-case thermal resistance measurements in an oven environment. A detailed discussion of the experimental errors and uncertainties is pre- sented. A figure of +4% has been obtained for both the accuracy and repeatability of an oven-based junction-to-case thermal resis- tance test method. This is shown to compare favorably with the performance of a temperature controlled heat sink system. By comparison with infra-red thermal imaging, the measurement of the average chip junction temperature is shown to provide an accurate thermal resistance figure for conventional IC package structures. IC packages used to demonstrate the application of the test system and test chips to thermal characterization include DIP’S, PGA’s, and chip carriers. I. INTRODUCTION RENDS in IC technologies are toward the fabrication T of IC’s with die sizes over 12-mm square and with chip power dissipations of 50 to 100 W/cm2. These advances are being driven by world-wide requirements for increased electronic system computing power and processing speeds in ever reducing product size. Such developments have resulted in a very significant level of research and development in ad- vanced packaging technologies including associated materials and cooling strategies. Associated with this research effort is the requirement for zyxwvuts in situ testing of the thermal performance of the packaging technologies and systems. In many cases, this testing must be done prior to the availability of functional IC’s. In other cases, adequate information regarding chip surface temperatures is not easily obtained from functional devices. As a result, thermal test chips are finding increasing application in the evaluation and characterization of advanced IC packaging technologies and their associated assembly, interconnect, and cooling systems. The need for thermal characterization has also resulted in an increasing number of companies investing Manuscript received March 16, 1992; revised July 13, 1992. This paper was presented at the SEMI-THERM VI11 Conference, Austin, TX, February 3-5, 1992. This work was supported by research projects from the Irish Science and Technology Agency, the European Community, and the European Space Agency. The author is with the National Microelectronics Research Centre, Univer- sity College, Cork, Ireland. IEEE Log Number 9202876. zyxwvutsrqponm 0 Mathuna resources in the development and application of thermal test systems. This paper will report on the development and analysis of an automated thermal test system for the characterization of current and future packaging technologies. The discussion is based on the application of the system in conjunction with a range of custom-designed thermal test chips. The system has been designed to undertake oven calibration of the on-chip temperature sensors as well as subsequent thermal resistance measurements both in an oven and on a temperature controlled heat sink. A detailed analysis of the accuracy of the test system is presented. The presentation is aimed at giving a practical discussion of the issues involved in developing the test system, applying it to temperature sensor calibration and thermal resistance measurements, and in defining the error analysis associated with the system. The application of the test system and the thermal test chips to the characterization of a range of packaging technologies is presented with an emphasis being placed on the evaluation of the test system repeatability and the test methods used. zyxwv 11. THERMAL zyx TEST CHIPS As part of an ongoing program of research into the charac- terization of the performance and reliability of IC packaging technologies at NMRC, a range of package performance monitoring test chips have been developed with dimensions of 2.5 mm (CMOSZ), 6 mm (PMOS3), and 9 mm (PMOS2) square [1], [2]. The PMOS devices have been designed and fabricated using a silicon PMOS fabrication process which includes a highly doped, N-type diffusion step to provide an ohmic contact in the substrate. zyxw An n-well CMOS process has been used in the CMOS2 design. Figs. 1 and Fig. 2, respectively, show photographs of the PMOS3 and CMOS2 test chips. The PMOS2 and PMOS3 devices are multisensor test chips which contain test structures for the evaluation of thermal resistance, electrical performance, corrosion, and thermome- chanical stress effects of packaging technologies. These multi- sensor test chips are similar in design concept to those recently developed by Sandia [3]. For thermal resistance measurements, structures on both devices consist of large area diffused resistors which are used as heat sources. Both the PMOS2 and PMOS3 test chips have been tested to 12 W. 0148-641 1/92$03.00 zyxwvutsrq 0 1992 IEEE