2236 IEEE TRANSACTIONS ON INFORMATION THEORY, VOL. 49, NO. 9, SEPTEMBER 2003 Simultaneous Zero-Tailing of Parallel Concatenated Codes Marten van Dijk, Sebastian Egner, Ravi Motwani, and Arie G. C. Koppelaar Abstract—In a parallel concatenated convolutional code, an information sequence is encoded by a convolutional encoder, and an interleaved version of the information sequence is encoded by another convolutional encoder. We discuss the situation in which we require both convolutional encoders to end in the all-zero state. To do so, we have to split an information word in two parts. One part contains the true information bits, and the second part contains the so-called tail bits, which are special bits with values com- puted such that both encoders end in the all-zero state. Depending on the interleaver, a different number of tail bits are needed. By using a construc- tive method, we give a characterization of all interleavers for a prescribed number of tail bits. We explain the method of encoding. In addition, simula- tions have been carried out to investigate the performance of codes resulting from simultaneous zero-tailing. This shows that simultaneous zero-tailing is similar in performance as compared to previously known zero-tailing methods (but with fewer trellis termination bits) and that it is better than zero-tailing just one of the encoders. Index Terms—Parallel concatenated codes, zero-tailing. I. INTRODUCTION Parallel concatenated convolutional codes (PCCC) are codes in which the encoder is as shown in Fig. 1. The convolutional encoders used have a recursive nature, which is shown to be necessary for the good performance of the iterative decoding of these codes [1]. In many communication systems, one wants to work on a frame base. Therefore, we need methods to make good block codes out of the parallel concatenated convolutional codes. One method, known from convolutional codes is zero-tailing, wherein the encoder starts in the all-zero state and is forced back to the all-zero state at the end of every frame. With a nonrecursive encoder this can be done by inputting zeros to the encoder ( being the memory of the encoder) at the end of the information sequence for every frame, whereas for a recursive convolutional encoder, these tail bits must have special values. With PCCC, we face the problem that forcing one encoder to the all-zero state does not imply that the other encoder will also end in the all-zero state. There are many ways for trellis termination of PCCC. It would def- initely not be advisable to just truncate the trellis of both or either of the convolutional codes, since this would imply that the free distance for both or either one of the convolutional codes is not guaranteed. For large interleaver sizes , it has been observed [1] that the difference between terminating only one encoder and terminating both encoders is insignificant. However, for the case of small and mid-size , both encoders need to be properly terminated. One way of zero-tailing the encoders is to substitute bits with specific values at specified places in Manuscript received January 9, 2002; revised April 23, 2003. The material in this paper was presented in part at the IEEE International Symposium on Information Theory, Sorrento, Italy, June 2000. This work was performed when all the authors were working for Philips Research Laboratories, Eindhoven, The Netherlands. M. van Dijk and S. Egner are with Philips Research Laboratories, 5656 AA Eindhoven, The Netherlands (e-mail: marten.van.dijk@philips.com; sebastian. egner@philips.com). R. Motwani is with the Electrical Engineering Department, Indian Institute of Technology, Kanpur, India (e-mail:motwani@iitk.ac.in). A. G. C. Koppelaar is with the Advanced Systems Laboratory, Philips Semiconductors, 5656 AA Eindhoven, The Netherlands (e-mail: arie.kop- pelaar@philips.com). Communicated by R. Urbanke, Associate Editor for Coding Techniques. Digital Object Identifier 10.1109/TIT.2003.815807 Fig. 1. An encoder for a parallel concatenated convolutional code. the information sequence such that both encoders end in the all-zero state. Forcing back the encoders to the all-zero state is preferred, since this ensures that the combined sequences and both have weight . Note that the component codes are not necessarily iden- tical such that the free distance of the two component codes may have different values. The required number of tail bits and their po- sitions depend on the interleaver used. In [2], a method is presented to zero-tail with tail bits ( and are the memory of the constituent codes). In [3]–[5], design of special interleavers requiring tail bits, which ensures that both encoders end in the same state is proposed. So, with only zero-tailing bits, both encoders can be forced back to the all-zero state, thus requiring a total number of bits for trellis termination. However, the class of interleaver proposed in [3], [4] is restricted, as shown in the next sections. Methods to look at the problem of jointly terminating the trellis of the PCCC in a more general way have also been observed in literature [5], [6]. Reference [7] summarizes the possible methods to terminate parallel concate- nated convolutional codes and also provides simulation results for the same. This tutorial paper discusses the effects of no trellis termination, terminating only one constituent code, and simultaneous zero-tailing. However, the conditions on interleavers for simultaneous zero-tailing obtained therein are again quite restricted. PCCCs with tailbiting tech- niques for trellis termination are discussed in [8], and also mentioned in [9]. In this correspondence, we give a characterization of interleavers which attain simultaneous zero-tailing with , tail bits. Hence, our class of interleavers with zero-tail properties is more general and larger than reported in literature. In Section II, we describe zero-tailing mathematically, and describe the method of encoding for simultaneous zero-tailing. The constraints which the interleaver has to satisfy in order to obtain zero-tailing for both encoders simultaneously are discussed in Section III. Construction methods for these interleavers are also discussed. With simulations, different zero-tailing strategies are compared in Section IV. II. SIMULTANEOUS ZERO-TAILING Let , be the information bits and let be the corresponding information sequence represented by the polynomial 0018-9448/03$17.00 © 2003 IEEE