D A DTMOS–BASED 1 V OPAMP H. F. Achigui, C. J.–B. Fayomi, M. Sawan PolyStim Neurotechnology Laboratory Electrical Engineering Dept., Ecole Polytechnique de Montreal E-mail: {herve.achigui-facpong, mohamad.sawan} @polymtl.ca; fayomi@grm.polymtl.ca ABSTRACT In this paper, we present a new opamp based on dynamic threshold voltage (DTMOS) transistors for low voltage applications (1–V). The opamp is a two stages configuration, with differential input pairs followed by a single ended class AB output. The input stage uses DTMOS devices for input common-mode range enhancement. The performed simulation shows a dc open loop gain of 64.4 dB, a phase margin of 64 o and unity gain frequency of 35.7 MHz under a 10 KΩ and 5 pF load, using the 0.18 µm CMOS technology. The opamp has a CMRR of 84 dB, input and output swings of 0.7 V and 0.9 V respectively. Index terms – DTMOS, CMOS analog integrated circuit, low voltage operational amplifier, differential amplifier. 1. INTRODUCTION ESIGN OF ANALOG IC’s operating at low voltages with high performance features has been gaining more and more importance during last decay, especially for applications such as medical electronic implants devices, portable and battery powered electronic devices. Communication large–scale integrations are predicted to target 1–V operation, and even less. However, the trends towards lowering the power supply voltage of circuitries in mixed-signal (digital/analog) signal environment often sacrifices their analogues counterpart in terms of speed, noise requirements and linearity. This poses a great challenge to CMOS mixed-signal circuits design. Reduction of threshold voltage is necessary for low voltage operation; on the other hand, the threshold voltage does not scale down with supply voltage of future standard CMOS technologies [1]. An obvious solution could be the use of multi-process threshold technology, but unfortunately, this kind of technology is more expensive and frequently not easy to reproduce. Some design advantages could be obtained by using BiCMOS technology, but at the expense of additional cost. Several design techniques have been proposed for realization of 1–V operational amplifier. In [2] the authors presented a design technique for facilitating 1–V operation based on bulk-driving architecture. However, substantially small input transconductance (g m ) is obtained compared to a conventional gate-driven MOS transistor and furthermore, the equivalent input referred noise is larger. Other rail-to-rail design techniques are presented in [3]–[5] using standard CMOS technology process. In [3], the authors used a level shifter, based on switched capacitors to provide the required dynamic bias voltage to the PMOS input transistors pairs, which is quite tremendous and tedious, even if it is suitable for switched capacitors applications. The major problem with other architectures in [4]–[5], based on the use of N-P complementary rail-to-rail input stage is the increase of the total harmonic distortion (THD) due to the dependence of the input offset voltage on the common mode input voltage swing. Since the first introduction of dynamic threshold voltage MOSFET (DTMOS) in 1994 [6], many novel interesting proposal circuits operating at low supply voltage have been made [7] and most of them achieved low threshold voltage by modifying the fabrication process, using the SOI technology. In this paper, a new class AB opamp is proposed for low-voltage applications. The circuit makes use of the DTMOS folded cascode differential input pair to increase the input common mode range (ICMR). Standard Miller compensation is used for bandwidth enhancement as illustrated in Figure 1. Following this introduction, section 2 focuses on the description of the opamp architecture with a focus on the DTMOS transistor. Section 3 is related to preliminary results and we conclude with section 4. 2. LOW-VOLTAGE DTMOS BASED OPAMP The proposed implementation includes a differential input stage and a class AB output stage capable of driving off chip resistive load. Biasing circuit consists of standard current source using a resistance and a NMOS transistor. A wide swing current mirror with high output impedance, is used to produce bias voltages V BP and V BN as presented in Figure 2 and Figure 3. 252 0-7803-8163-7/03/$17.00 © 2003 IEEE ICECS-2003