1 Design and Characterization of Low-Voltage Analog Switch Without the Need for Clock Boosting Christian Jésus B. FAYOMI Université du Québec à Montréal Computer Science Department Microelectronics Laboratory, President Kennedy Hall 201 President Kennedy Avenue, Montreal, CANADA H2X 3Y7 Gordon W. ROBERTS McGill University Department of Electrical and Computer Engineering McConnell Engineering Building 3480 University Street, Montreal, CANADA H3A 2A7 ABSTRACT This paper deals with design and characterization techniques of a low-voltage CMOS analog switch to be used in sample-data circuits. Hspice simulation-based simple design procedure and a characterization method are presented. The switch on- resistance, the error voltage caused by charge injection and clock feedthrough as well as non-linear distortion simulation approaches are proposed. The procedure has been applied to the design of a CMOS transmission gate operating at a 10 MHz clock signal under a 1.8 V supply voltage in a 0.18 m digital CMOS process. The proposed method is suited for a pencil-and- paper design. Its accuracy is limited only by the numerical accuracy of Hspice. 1. INTRODUCTION Analog switches are a common building block in analog signal processing. They are used for signal routing in multiplexers and filter selection and to apply reference voltages or currents for calibration systems, for gain selection in programmable-gain amplifiers (PGAs) and switching demodulators, for signal samplings in sample-and-hold systems (SHAs), and in flying capacitor amplifiers (or switched capacitors) and multiplexers. In most of those applications they must achieve high speed and high linearity with high precision. In most applications, the analog switch performs a sample-and-hold function and introduces error voltage that occurs when the device is turned off. In SHA circuits, the error in the sample voltage is caused by two charge transport mechanisms. These are called charge injection and clock feedthrough [1]. For a nMOS (respectively pMOS) switch, negative (respectively positive) charge is added to the sample voltage as the nMOS (respectively pMOS) switch is shut off, causing a negative (respectively positive) error voltage. The charges stored in the channels of the n- and p-type transistors have opposite polarities. Therefore the charge injections, due to the overlap capacitances, have opposite polarities for the two transistors. Several methods have been proposed to overcome these problems, such as charge cancellation by a dummy MOS transistor and an offset cancellation by adding a compensation network [2]. Although charge cancellation methods that make use of a dummy transistor produce good simulation results, great care must be exercised when laying out the clock tree controlling the complementary switches. Other methods have either limited input bandwidth or introduced high design complexity. Distortion and noise mechanisms are responsible for limiting the dynamic range of most electronic circuits. With the ever-increasing demand for higher resolution signal processing, lower operating voltages and shorter design cycles, it is important to be able to quantify the effect of these two mechanisms prior to implementation. For the most part, in the case of continuous-time circuits, Hspice is equipped to provide such information, e.g., .FOUR and .NOISE commands. For sampled-data circuits, no such tool exists that can provide such data, although one is beginning to see some developments for predicting the noise behaviour of linear sampled-data circuits [3]. In this work we will demonstrate how pencil-and-paper design combined with Hspice can be used to compute the on- resistance, the error voltage caused by charge injection and clock feedthrough as well as non-linear distortion. We will start by a brief review of the basic principle of the analog switch in Section 2 with main parameter design equations. Section 3 will provide a simple Hspice design example to demonstrate the application and we will conclude in Section 4. 2. ANALOG SWITCH DESIGN CONSIDERATIONS A fundamental component of any dynamic circuit (analog or digital) is the switch. The drain and source are the two switch terminals and the gate (and sometimes the bulk) [1] are used to control the conductivity. An important attribute of the switch in CMOS is that under DC conditions, the gate of the MOSFET does not draw a current. Therefore, neglecting capacitances from the gate to drain/source, we find that the gate control signal does not interfere with the information being passed through the switch. Ideally, the switch in the on state acts as fixed linear conductance g ds . In practice, however, the conductance is strongly signal-dependent. Equation (1) gives the conductivity of the transistors as a function of the power supply voltage V DD and the input signal: pMOS nMOS , , p th in p ox p n th in DD n ox n ds V V L W C V V V L W C g (1) C ox is the capacitor of the gate-oxide, V th,n and V th,p are respectively the threshold voltage of the n- and p-type transistors, n and p are respectively electron and hole mobility in both types of transistors. The bulk of the nMOS and pMOS transistors are respectively connected to V SS and V DD unless otherwise stated. The plot in Figure 1 shows the small signal conductance as a function of a source voltage. The switch conductance through the whole range of input is not constant, and depends on the supply voltage. It appears that a pMOS (respectively nMOS) switch exhibits an on-conductance that increases (respectively decreases) as the input voltage becomes more positive. The largest voltage a n-channel switch can pass is V DD -V th,n , while the lowest voltage a p-channel switch can pass is |V th,p |. The benefits of using the CMOS transmission gate (TG) are seen from this figure, namely, lower overall conductance. Another benefit of using CMOS TG is that it can pass logic high or