342 IEEE ELECTRON DEVICE LETTERS, VOL. 24, NO. 5, MAY 2003 Fully-Depleted SOI Devices With TaSiN Gate, HfO Gate Dielectric, and Elevated Source/Drain Extensions A. Vandooren, A. Barr, L. Mathew, T. R. White, S. Egley, D. Pham, M. Zavala, S. Samavedam, J. Schaeffer, J. Conner, B.-Y. Nguyen, Bruce E. White, Jr., Member, IEEE, Marius K. Orlowski, Fellow, IEEE, and J. Mogab Abstract—We report for the first time performance of ultra- thin film fully-depleted (FD) silicon-on-insulator (SOI) CMOS transistors using HfO gate dielectric and TaSiN gate material. The transistors feature 100–150 silicon film thickness and selective epitaxial silicon growth in the source/drain extension regions. TaSiN-gate shows good threshold voltage control using an undoped channel, which reduces threshold voltage variation with silicon film thickness and discrete, random dopant placement. Device processing for CMOS fabrication is drastically simplified by the use of the same gate material for both n- and p-MOSFETs. Electrical characterization results illustrate the combined impact of using high dielectric and metal gate on the performance of ultrathin film FD SOI devices. Index Terms—CMOSFETs, high , metal gate, silicon-on-insu- lator technology. I. INTRODUCTION T HIN fully-depleted (FD) silicon-on-insulator (SOI) MOS- FETs have many advantages, over bulk devices, such as re- duced junction capacitance, immunity to radiation and latch-up, and process simplicity. They are also attractive candidates for deep submicron applications because short channel effects can be suppressed by reducing the silicon film thickness and by con- current scaling of the buried oxide thickness [1], [2]. This al- lows the use of very low doping concentration in the channel, which offers the additional advantages of enhanced mobility, reduced junction leakage, and suppression of dopant fluctua- tion effects. The threshold voltage variation due to the silicon film nonuniformity is also reduced by using a low doping in the channel. However, the threshold voltage needs to be ad- justed by the work-function of the gate material. Metal gates with work-function close to midgap, such as TiN and Ta, have been previously proposed [3], [4]. Metal gates offer the addi- tional advantages of 1) suppression of polysilicon depletion ef- fects, 2) elimination of boron penetration, and 3) reduction of the gate sheet resistance. TaSiN is a very attractive candidate be- cause it exhibits low resistivity, very good thermodynamic sta- bility, good chemical durability to wet chemical cleaning, and is a diffusion barrier for copper. In this paper, we describe TaSiN gate ultrathin film 100–150 FDSOI CMOSFETs [5] with good threshold voltage adjustment on low doped SOI layers. We Manuscript received January 7, 2003; revised February 27, 2003. The review of this letter was arranged by Editor C.-P. Chang. The authors are with Motorola, Inc., Austin, TX 78721, USA (e-mail: anne.vandooren@motorola.com). Digital Object Identifier 10.1109/LED.2003.812525 Fig. 1. TEM micrograph of the FDSOI device x-section and HR-TEM micrograph of the FDSOI device gate stack and silicon channel (inset). successfully integrate HfO gate dielectric while maintaining low interface trap density and good subthreshold characteristics. Elevated source/drain extensions structures are used to lower the series resistance due to the thin silicon film thickness. II. DEVICE FABRICATION The devices were fabricated on standard UNIBOND 1 SOI wafers with a silicon film thickness of 110 nm and a buried oxide thickness of 200 nm. The superficial silicon was thinned down to 200 by successive thermal oxidation and oxide wet-etch. The transistor channel was left undoped with a p-type background concentration cm . Shallow trench isolation was used. HfO gate dielectric was deposited by MOCVD at 550 C, resulting in a 12 interfacial layer and a 35 HfO dielectric stack (Fig. 1, inset). PVD TaSiN was then reactively sputtered to form the gate electrode. A nitride liner was deposited and, after HfO removal from the SD regions, a 300 -thick selective epitaxial silicon was grown in the extension regions at 800 C. After gate patterning, P and was implanted in the exten- sions. Cobalt silicidation and copper backend processing were used. After completed processing, the silicon film thickness in the channel was approximately 100–150 . The control of the silicon film thickness uniformity and defectivity are potential issues for very thin films, as the uniformity degrades when the silicon film is thinned down. A 25–30% silicon film thickness variation was measured at 200 silicon film, corresponding 1 UNIBOND is a registered trademark of SOITEC. 0741-3106/03$17.00 © 2003 IEEE