At-Speed Built-in Self-Repair Analyzer for Embedded Word-Oriented Memories Abstract CRESTA is a built-in self-repair analyzer (BISRA) used for repair of bit-oriented memories, which can repair all repairable bit-oriented memories with available spare resource. This paper enhances CRESTA to support embedded word-oriented memories. Within each read cycle of at-speed memory BIST, the analyzer is able to handle multiple-bit failure in a word-oriented memory. Furthermore, to reduce area overhead, the proposed analyzer is reconfigurable to process all repair strategies in serial. To cover all repair strategies efficiently, we propose a branch and bound algorithm to select repair strategies. 1. Introduction The percentage of chip area occupied by embedded memories in current System on Chip (SOC) designs is more than 50% and is expected to rise to 94% by year 2014 [1]. Thus the yield of embedded memories is expected to determine the yield of SOCs. Recently, due to larger embedded memories and the higher probability of defects in SOCs using deep sub-micron technologies, use of redundancy to increase yield is gaining popularity. To repair defective memories, spare rows or spare columns are placed in a memory to replace defective rows or columns in the memory. Recently, several papers [2-5] have proposed built-in self repair analyzers (BISRA) to achieve at-speed repair analysis during manufacture test of SOCs. Based on the failure information detected during its build-in self-test (BIST), a BISRA is used to determine how to repair a memory with its redundancy to cover all faulty cells. The determined repair information can be sent to the on-chip repair logic or repair equipment that does the actual physical repair [7]. Since the failure information can be huge, it is not realistic to store all failure information in a BISRA. Therefore, a BISRA has to decide whether to use a spare row or a spare column when each failure is detected. Here, we call the allocation order of spare rows and spare columns as a repair strategy. The repair strategies analyzed may be pre-selected [8] or all repair strategies feasible with the given spare resources are all processed simultaneously [5]. In [2], the authors used spare column only repair that simplified self-repair scheme. However the method will not repair word-line failures. The repair strategy of [3] accommodates only the case of one spare row and one spare column for self-repair of a memory block or segment. In [4], the repair strategy uses two sets of spare resources in SRAMs: one spare row and one spare column, and two spare rows and two spare columns. A spare row is used whenever more than one defective cell is discovered in a row in one read cycle. This strategy avoids the use of available two spare columns to repair the failures detected at one time in the word. However this strategy does not repair some memories that can be repaired using the available spare resources. In [5], the authors proposed a repair scheme called CRESTA (Comprehensive Real-time Exhaustive Search Test and Analysis) for bit-oriented memories. It processes all possible repair strategies simultaneously and each repair strategy is processed in one sub-BISRA. So this method guarantees finding a solution for a bit-oriented memory that can be repaired using the available spare resources. A Memory BIST engine is used with BISRA to apply tests and to analyze test responses to determine memory defects. A Full-Speed TM MBIST [9] uses pipelines within the BIST controller such that it can launch read or write operation every cycle. So it is possible that faults may be detected in every cycle. It is also possible to detect more than one bit failure in the same word at the same time for a word-oriented memory. So the BISRA has to handle multiple-bit failure within one cycle. If spare column is used, it is impossible to figure out how many spare columns are needed in one cycle. Although one can suspend the memory BIST temporarily to handle failures one by one in a word with multiple defects, it is not suitable for at-speed test. In this paper, we will present a new BISRA with improvements in several ways. It is able to handle the case when multiple-bit-failure in a word is detected at one time. To reduce area overhead, the proposed analyzer is reconfigurable to process all repair strategies in serial. To cover all repair strategies efficiently, we propose a branch and bound algorithm to select repair strategies. The remaining sections of the paper are organized as follows. In Section 2 we describe memory architectures. In Section 3 we develop BISRA algorithms for different memory architectures. In section 4 we describe the Xiaogang Du Sudhakar M. Reddy ECE Department University of Iowa Iowa City, IA 52242 Wu-Tung Cheng Joseph Rayhawk Nilanjan Mukherjee Mentor Graphics Corporation 8005 SW Boeckman Road, Wilsonville, OR97070 Proceedings of the 17th International Conference on VLSI Design (VLSID’04) 1063-9667/04 $ 20.00 © 2004 IEEE