Advanced Verification by Automatic Property Generation Frank Rogin 1 Thomas Klotz 1 Görschwin Fey 2 Rolf Drechsler 2 Steffen Rülke 1 1 Fraunhofer Institute for Integrated Circuits, Division Design Automation, 01069 Dresden, Germany {frank.rogin,thomas.klotz,steffen.ruelke}@eas.iis.fraunhofer.de 2 University of Bremen, Institute of Computer Science, 28359 Bremen, Germany {fey,drechsle}@informatik.uni-bremen.de January 12, 2009 Abstract Property checking is a promising approach to prove the correctness of today’s complex designs. However, in practice this requires the formulation of formal properties which is a time consuming and non-trivial task. Therefore, the acceptance and efficiency of formal verification techniques is increased by an automated support for formulating design properties. In this paper we propose a new methodology to automatically generate com- plex properties for a given design 1 . The tool Dianosis implements this methodology by analysing a simulation trace and extracting properties. Complex properties describe the abstract design behaviour and improve design understanding, e.g. by discussing them with the particular designers or reflecting them to the specification. The properties are presented in a format that is easy to read and they can be used as a basis for the application of for- mal or assertion-based verification techniques. We provide experimental results on industrial hardware designs that show the effectiveness of Dianosis and motivate the practical use. 1 Introduction The conventional simulation-centred verification methodology is insufficient to meet today’s requirements, such as an exhaustive verification of complex designs, or the demand for first-time-right designs [2, 3]. As verification has become the dominating factor in circuit and system design, huge efforts have been made in the past to increase the productivity and quality of the verification process. New formal [4–6] and semi-formal verification tech- niques [7,8] were proposed over the past few years and some of them are now part of recent industrial design flows (e.g. equivalence checking [9]). Furthermore, verification techniques such as property checking or assertion-based verification are gaining increased acceptance in the semiconductor industry. All of these techniques, however, require a formal specification of the design. For that, properties have to be defined manually which is an error-prone and non-trivial task. They are normally derived from a high-level specification written in natural language that may contain inconsistent, erroneous, or incomplete requirements. The scalability of property languages to large designs, the complexity of temporal logics, and the difficult consistent formulation of properties often hamper a widespread application of formal techniques [10]. Moreover, complex properties expressing the inter-module interaction are hard to write. The increasing design complexity and a distributed development process additionally complicate this task. So, any method to reduce the effort of writing properties and in particular to abstract the design behaviour is welcome. Particularly, this could help to increase the acceptance of formal techniques. 1 A preliminary version of this paper was presented at DATE’08 [1]. 1 This paper is a postprint of a paper submitted to and accepted for publication in IET Computers & Digital Techniques and is subject to Institution of Engineering and Technology Copyright. The copy of record is available at IET Digital Library.