A Flexible Approach to High Level Simulation of Complex System-on-Chip Muhammad Usman Ilyas § Department of Computer Science, Lahore University of Management Sciences, Lahore 54792, Pakistan Email: muilyas@lums.edu.pk Syed Ali Khayam § Department of Electrical & Computer Engineering, Michigan State University, East Lansing, MI 48824, USA Muhammad Omer Suleman § Computing Laboratory, Oxford University, Oxford OX1 3DQ, United Kingdom Shahid Masud Department of Computer Science, Lahore University of Management Sciences, Lahore 54792, Pakistan § These authors were previously at AVAZ Networks, Software Technology Park, Constitution Avenue, Islamabad, Pakistan Abstract – This paper presents a method to create a model for simulating the top-level system design of System-on-Chip using a sequential language. The model constitutes a cycle accurate simulation of the system under test at the required level of abstraction. The need for such a configurable platform arises during the initial system level design phase. The approach described in the paper has been successfully applied in the system level verification of a commercial media processor where the primary application is in VoIP media gateways. The implementation is primarily focused on monitoring and verification of inter-processor communication (IPC) among processing engines in the media processor. I. Introduction For years now verification teams of large projects have been struggling to keep up with the increasing gate count of complex ASICs. Project managers need to allocate more and more time to verification and testing phase in the design cycle. The complexity of System-on-Chip (SOC) is now well above ten million gates [1]. The requirement of extensive simulation and testing for this kind of gate complexity has led to a scheme whereby complex hardware modules of the system are replaced with simplified Bus Functional Models (BFM) during verification [2]. The verification and testing of SOC designs takes up a significant fraction of product development cycle. The designs have to be simulated and tested at different levels at different stages of development. First the design is tested functionally during the initial system level design stage and later a more detailed testing is done at register transfer level using the RTL code. Simulations at both levels of detail are traditionally implemented in Hardware Description Languages (HDL) [3]. II. Traditional Simulation Techniques The verification of complex SOC designs is done using a combination of RTL and high-level behavior description in an HDL such as Verilog or VHDL. Traditionally both the high-level system design as well as the low-level register transfer level testing is done using models implemented in HDL [4]. However, testing using HDL models has following two major disadvantages: a. An HDL simulation executes at a much slower rate compared to an equivalent piece of code in a sequential language that is functionally identical, and b. Additional cost of the HDL software tools and the computer platforms required to execute them is significant. The work presented in this paper addresses both these issue through the replacement of high-level system components by their respective BFM. These functional models not only speed-up the design cycle by orders of magnitude but result in significant reduction in the overall design cost. The rest of the paper is organized as follows: Section III outlines the development of the BFM approach for SOC functional testing. Section IV discusses the application of this approach in a VoIP media multiprocessor SOC development. Section V presents the results followed by conclusions. III. Outline of the Model An alternative to using detailed RTL code implemented in HDL is the use of models implemented in sequential languages [5, 6]. This section describes how the BFM model was successfully implemented in a sequential language (Visual C++). Listed below is a list of features of the model.