International Journal of Latest Research in Engineering and Technology (IJLRET) ISSN: 2454-5031 www.ijlret.com || Volume 02 - Issue 05 || May 2016 || PP. 69-73 www.ijlret.com 69 | Page DESIGN OF DIFFERENT DEVICES USING BICMOS LOGIC Divya Bora M.Tech VLSI G.H.Raisoni Institute Engineering And Technology For Women, Nagpur. Dr. U. M. Gokhale Electronics and Telecommunication G.H.Raisoni Institute Engineering And Technology For Women, Nagpur. ABSTRACT- By integrating two separate semiconductor devices that are bipolar junction transistor and CMOS transistor, in single integrated circuit devices which make a new semiconductor technology that is BiCMOS technology. As BiCMOS technology have several advantages like large load driving capabilities, low static power, fast switching, high gain, low noise and low output impedance. This paper presents the design and simulation of digital circuits such as logic gates, half adder, full adder which are basic components used for designing any other circuits such as multipliers, processors etc. These circuits are designed using BiCMOS logic and proposed designs are designed and simulated on TANNER EDA. KEY WORDS- CMOS, Power dissipation, latch up, BiCMOS, logic gates, adders, TANNER Tools. I. INTRODUCTION In 1930, when Lienfed and Heil introduces about MOSFETs, the history of semiconductor devices are started. To make their idea come true in reality it take 30 years, and up to the late 1980 this trend took a turn when MOS technology caught up. CMOS was finding more wide spread use due to its low power dissipation, high packing density and simple design, by the year 1990 the 90% of total MOS are covered by CMOS. In 1983 bipolar compatible process based on CMOS technology was developed and in 1990’s BiCMOS technology with both the MOS and bipolar device fabricated on the same chip was developed and studied. The main objective of introducing the BiCMOS technology is to combine BJT and CMOS technologies so as to exploit the advantages of both at the circuit and system levels. Since 1985, the state-of-the-art bipolar CMOS structures have been converging. Using this technology in reality by exploiting their advantages, now BiCMOS has become one of the dominant technologies which used for high speed, low power and highly functional VLSI circuits especially when the BiCMOS process is as similar as the CMOS process without adding any additional step to it. Because the process step required for both CMOS and bipolar are same and these steps can be shared for both of them. II. LATCH UP IN CMOS Traditionally uses the specific CMOS buffer circuits which have the enhanced driving capability to solve the problem driving large load. But most of the buffer configurations require a significant amount of silicon area for improvement in the signal propagation delay. The serious problem associated in CMOS devices is Latch up condition. As CMOS is having advantages of low static power consumption and the advantage of BJT that is the high current driving capabilities, the BiCMOS logic combines the both advantages into one IC. Latch up condition The latch-up condition is happens at any place where the required parasitic structure exists. A semiconductor goes to high current state when there is an interaction between PNP and NPN transistor causes latch up in CMOS devices. Due to latch up in any CMOS circuit cause the damage device into a loss of data or sometimes device itself. Latch up can initiate thermal runaway and can lead to destruction of a semiconductor package, chip or system when these parasitic pnpn elements undergo a high current state. Reducing the CMOS power supply voltage is a potential solution for hard latchup failures, but not soft ones [10].This condition of CMOS logic is overcome by BiCMOS logic and so using BiCMOS logic we are designing different devices.