Interconnect intellectual property for Network-on-Chip (NoC) Jian Liu * , Li-Rong Zheng 1 , Hannu Tenhunen 2 Laboratory of Electronics and Computer Systems (LECS), Royal Institute of Technology (KTH), Institute of Microelectronics and Information Technology (IMIT), Electrum 229, SE-164-40 Kista, Stockholm, Sweden Abstract As technology scales down, the interconnect for on-chip global communication becomes the delay bottleneck. In order to provide well-controlled global wire delay and efficient global communication, a Network-on-Chip (NoC) architecture was proposed by different authors [Route packets, not wires: on-chip interconnection networks, in: Design Automation Conference, 2001, Proceedings, p. 684; Network on chip: an architecture for billion transistor era, in: Proceeding of the IEEE NorChip Conference, November 2000; Network on chip, in: Proceedings of the Conference Radio vetenskap och Kommunication, Stockholm, June 2002]. NoC uses Interconnect Intellectual Property (IIP) to connect different resources. Within an IIP, the switch has the central function. Depending on the network core of the NoC, the switch will have different architectures and implementations. This paper first briefly introduces the concept of NoC. It then studies NoC from an interconnect point of view and makes projections on future NoC parameters. At last, the IIP and its components are described, the switch is studied in more detail and a time–space–time (TST) switch designed for a circuit switched time-division multiplexing (TDM) NoC is proposed. This switch supports multicast traffic and is implemented with random access memory at the input and output. The input and output are then con- nected by a fully connected interconnect network. Ó 2003 Elsevier B.V. All rights reserved. 1. Introduction Interconnect has been the major design con- straint in deep sub-micron (DSM) circuits. The downscaled wire size, increased aspect ratio, combined with higher signal speed cause many signal integrity challenges and timing closure problems. Traditionally, these issues are tackled mainly from an electrical design point of view. Recent studies show that the problem also can be coped with interconnect-centric system architec- tures [2,7,8]. One such emerging architecture is the Network-on-Chip (NoC). The NoC architecture is a data packet based communication network on a single chip. It scales from a few dozens to several hundreds resources. A resource may be a processor core, a DSP core, an FPGA block, or any other intellectual property (IP) block. The resources are connected by Interconnect IPs. The structured network wiring gives well-controlled electrical pa- rameters and enables reusing of building blocks. Clearly, any topology that fully connects the * Corresponding author. Tel.: +46-8-790-4197; fax: +46-8- 751-1793. E-mail addresses: jianliu@imit.kth.se (J. Liu), lrzh- eng@imit.kth.se (L.-R. Zheng), hannu@imit.kth.se (H. Tenh- unen). 1 Tel.: +46-8-790-4104. 2 Tel.: +46-8-790-4119. 1383-7621/$ - see front matter Ó 2003 Elsevier B.V. All rights reserved. doi:10.1016/j.sysarc.2003.07.003 Journal of Systems Architecture 50 (2004) 65–79 www.elsevier.com/locate/sysarc