Introducing a technology index concept and optimum performance design procedure for single-electron-device based circuits Mohammad Javad Sharifi a,n , Davoud Bahrepour b a Faculty of Electrical and Computer Engineering, Shahid Beheshti University, Velenjak, Tehran, Iran b Science and Research Branch, Islamic Azad University, Tehran, Iran article info Article history: Received 15 October 2010 Received in revised form 27 January 2011 Accepted 27 April 2011 Keywords: Optimum design procedure Technology index Single electron device Digital gate abstract Single electron devices (SEDs) are utilized in designing many logic gates; however, in most cases the examination of the circuits is limited to a DC analysis that only indicates the correct performance of the circuits’ logic function. This paper focuses mainly on the issue of optimization. In this regard, comparison of different designs is needed, but it is not possible to compare two different designs unless they both belong to a single technology or can be scaled to a same technology. So, we first introduce a technology index for SEDs, which allows meaningful comparisons between various designs of different technologies. Then, we describe a method for scaling these designs into a single identical technology, and clarifying the relations between the involved concepts. Using two examples, we explain an optimum design method for digital logic gates based on SEDs. Finally, the results of these two examples are presented and compared with the original designs. The comparison showed that all the three major performance features, including lower bit error rate, higher operation frequency, and higher temperature operation are improved in the proposed optimized design. & 2011 Elsevier Ltd. All rights reserved. 1. Introduction Due to their ultra small dimensions and lower power con- sumption, single-electron devices (SEDs) are good candidates for future ULSI applications. Although they are utilized in many digital logic gates [1–7], gate operation is usually examined merely by a simple verification using SIMON [8], and optimum design procedures are either less studied or the procedures presented are incomplete [9–11] or very complex [12]. This paper aims to present a method for achieving optimum performance of SED-based digital gates by introducing a simple quality index. In Section 2, the technology concepts are discussed and a technology index for SEDs is introduced. In Section 3, we consider a NOT gate as our first example and propose a design procedure for optimum gate performance. This design procedure is based on a single index, the quality index, that characterizes the perfor- mance. The design procedure and optimum design will be repeated for a NAND gate, as the second example, in Section 4. Finally, conclusions are provided in Section 5. 2. Technology index and scaling For any comparison between the performances of two differ- ent designs to be valid, the first important parameter is that the two designs must be implemented in a same technology. In other words, comparison of two designs, which are implemented in two different technologies, is not valid unless the two designs are scaled into a single technology. Therefore, we need an index for SED technology. 2.1. Introducing the technology index On one hand, a good technology index should be based on real technological limitations, and on the other hand, it should also have a clear relation with the performance of the circuits that are based on that technology. A well-known technology index is the minimum feature size for MOSFET technology. This indexes MOSFET technology in an excellent fashion because it not only reveals the most important limitations of the technology but it also has a clear relation with MOSFET circuit performances. Here, regarding SEDs and the two technology index criteria mentioned above, we intro- duce the total capacitor of the island, C T , and the tunneling resistor, R T , as the technology index. These two parameters are related to the SEDs’ technological limitations; because C T reveals the possibility of miniaturization and R T is associated with the technology’s manu- facturing tolerance, which is of growing importance. As we see later, Contents lists available at ScienceDirect journal homepage: www.elsevier.com/locate/mejo Microelectronics Journal 0026-2692/$ - see front matter & 2011 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2011.04.014 n Corresponding author. Tel.: þ98 9123045891; fax: þ98 21 29902284. E-mail addresses: m_j_sharifi@sbu.ac.ir (M. Javad Sharifi), bahrepour@ieee.org (D. Bahrepour). Microelectronics Journal 42 (2011) 942–949