IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 47, NO. 5, OCTOBER 1998 1385 Measurement System for a Preliminary Characterization of Flash Memory Cells for Multilevel Applications Giovanni Bucci, Member, IEEE, Marco Faccio, Member, IEEE, Carmine Landi, Member, IEEE, and G. Marotta Abstract—In this work a low-cost measurement system suitable for analog characterization of standard Flash memory cells is presented. Our aim, with this system, is to investigate the possi- bility of using standard cells for multilevel storage, to increase the bit density of conventional memory devices. Preliminary investigation was carried out by using a measurement system based on stand-alone instrumentation linked to a controller via IEEE 488 bus. The preliminary characterization results of the Texas Instruments TMS29FO40 4-Mbit Flash Memory show that it is feasible to store and retrieve information with four levels of injection charge in a single cell. Currently, a first multilevel test chip is under development. At the same time, a new measurement system, specifically suited to debug and test this special device, is under implementation. Index Terms—Automatic testing, component characterization, measurement system, memories, testing. I. INTRODUCTION R ECENT advances in nonvolatile memory technology have enabled the expansion of Flash memory into a wide variety of markets and products. Some applications are portable computers, wireless telephones, digital audio recorders, network routers, and patient medical monitors. In the instrumentation field, memory cards for data acquisition and embedded code storage are the main applications. The increasing need for additional nonvolatile data storage creates demand for higher density Flash products. In industry and academies, research is on-going to increase the Flash memory density. Besides technological minimum feature scal- ing, a novel approach aimed at storing more than one bit per cell is being pursued. Companies like Sandisk and Intel have already announced products featuring two-bit-per-cell storage for market release in 1998. An elementary cell, where the number of bits stored is greater than one, is commonly known as multistate or mul- tilevel in the engineering literature. This technology requires an increase in the number of different levels of charge on a floating-gate transistor [1], [2]. While this solution appears very attractive from a theoretical point of view, its imple- mentation presents some problems. For example, the increase in the number of levels reduces the voltage difference be- Manuscript received May 18, 1998; revised December 10, 1998. G. Bucci, M. Faccio, and C. Landi are with the Dipartimento di Ingegneria Elettrica, Universit` a di L’Aquila, Localit` a Monteluco, 67040 L’Aquila, Italy. G. Marotta is with Texas Instruments Italia S.p.A., 67051 Avezzano, L’Aquila, Italy. Publisher Item Identifier S 0018-9456(98)09878-7. tween the logic states thus requiring programming and reading circuits with higher resolution and accuracy than those used in conventional memories. Moreover, the production process must be reproducible to ensure a low narrow distribution of cell characteristics, and sophisticated algorithms are required to achieve reliable operation (read/write) throughout operating conditions and product lifetime. The multilevel Flash introduces additional complexity in characterization and testing, to account for the analog nature of the storage mechanism. The main purpose of the test system is to control and verify the charge injection on the floating gate of the Flash memory cell with sufficient accuracy to perform reliably multilevel writing and reading procedures. In this work, a measurement system, suitable for the analog characterization of standard Flash memory cells, is presented. The setup has been used to characterize a standard Flash chip, the Texas Instruments TMS29FO40, to study the floating-gate cell and memory behavior toward a multilevel application [3]. Based on the obtained results, the specification for an improved measurement system was also identified. This new system will allow the multilevel test chip under development to be debugged and tested during the engineering evaluation phase. II. THE CHARACTERIZATION OF A FLASH CELL Flash memories generally encode a single bit per cell as the electrical charge in the MOS floating-gate (FG) cell (also FAMOS–Floating gAte MOS cell). Each cell, or transistor, is characterized by a threshold voltage : two possible voltage levels then exist, for the two stored logic levels (empty FG or charge-injected FG). The injected charge is permanently stored and raises the threshold voltage of the device. If the floating-gate is above a certain reference level, the cell is considered to be in a different level (programmed). To obtain first reference information on analog behavior of the FG cell, we investigated the standard Flash Texas Instruments TMS29FO40, produced with a 0.5- m CMOS process technology. This is a 4-Mbit NOR type Flash memory, based on the source erase technology. In the Fig. 1, the internal NOR array architecture is shown. We accessed the matrix cells by using a special test mode in order to guarantee the external control of word-line and bit- line. The nominal procedures to supply the memory with write, erase, and read capabilities are described in the following. 0018–9456/98$10.00  1998 IEEE