Using Activation Intervals for Low Power Analysis Achim Rettberg, Bernd Kleinjohann, Wolfram Hardt University Paderborn / C-LAB, 33095 Paderborn, Germany Tel: +49 5251 606110, Fax: +49 5251 606065 Email: {achcad, bernd, hardt}@c-lab.de Abstract This paper describes a new approach to integrate low power methods in a design on architectural level. Starting from an asynchronous architecture presented as a data-flow graph, an activation interval analysis is conducted. The activation intervals describe a possible partitioning of a synchronous design. Each activation interval is a partition which is guarded by a gated clock. The transferability from the asynchronous to the synchronous design paradigm should be considered during the design phase. Gated clocks allow to switch off passive parts of the design and therefore support the saving of power consumption. 1 Introduction Today overall power consumption of electronic devices plays a major role. The electronic device market demands a permanently increasing time of utilization of the devices without charging the batteries. The extension of the durability reaches today’s limits of batteries. Switching off the display is another method to reduce power consumption. Similar methods are used for all components interior a device today. An exception for the devices shows the motherboard of a system and the used micro- processors on the board. The overall power consumption of a motherboard from a laptop is 52 percentage [1]. Therefore, power saving of board or chip design is very important. 2 Related Work Power is the rate, at which energy is delivered or exchanged [2], [4]. During operation electrical energy is converted to heat energy. The rate, at which energy is taken from the source (V dd ) and converted into heat, is called power dissipation. The power consumption of a chip is calculated by statistical methods or by abstractions [7]. It is a fact that there exists different approaches of power savings in systems [3], [6], [8]. The optimization for low power design can be classified into two main areas: • technology optimizations • software and compiler optimizations for programmable systems Technology optimizations are different cell optimizations e.g. dynamic power consumption, short circuit, leakage and static current. Additionally, other technology optimizations deal with adiabatic design. Reduction of the supply voltage V dd on the one hand lowers energy but on the other hand increases the delay. Software optimizations for low power go along with modifications of corresponding structure of an algorithm [8]. Modifications are necessary to decrease the total number of required operations, to substitute some operations with more convenient ones or to reduce word-length for data representations. All these modifications are integrated in compilers. Another low power compiler technique addresses the usage of cache or memory access.