LETTERS Spin-based logic in semiconductors for reconfigurable large-scale circuits H. Dery 1 , P. Dalal 1 ,L / . Cywin ´ski 1 & L. J. Sham 1 Research in semiconductor spintronics aims to extend the scope of conventional electronics by using the spin degree of freedom of an electron in addition to its charge 1 . Significant scientific advances in this area have been reported, such as the development of diluted ferromagnetic semiconductors 2,3 , spin injection into semiconductors from ferromagnetic metals 4–8 and discoveries of new physical phenomena involving electron spin 9,10 . Yet no viable means of developing spintronics in semiconductors has been presented. Here we report a theoretical design that is a conceptual step forward—spin accumulation is used as the basis of a semi- conductor computer circuit. Although the giant magnetoresistance effect in metals 11,12 has already been commercially exploited, it does not extend to semiconductor/ferromagnet systems, because the effect is too weak for logic operations. We overcome this obstacle by using spin accumulation rather than spin flow 13–15 . The basic element in our design is a logic gate that consists of a semi- conductor structure with multiple magnetic contacts; this serves to perform fast and reprogrammable logic operations in a noisy, room-temperature environment. We then introduce a method to interconnect a large number of these gates to form a ‘spin com- puter’. As the shrinking of conventional complementary metal- oxide–semiconductor (CMOS) transistors reaches its intrinsic limit, greater computational capability will mean an increase in both circuit area and power dissipation. Our spin-based approach may provide wide margins for further scaling and also greater computational capability per gate. At present, spintronics is realized only in all-metallic systems for applications in magnetic field sensing and non-volatile storage 16 . There have been only a few proposals to use logic gates in all-metallic magnetic systems 17–21 . Progress in this field was made possible by the discovery of the giant magnetoresistance effect in heterostructures of ferromagnetic and paramagnetic metal layers 11,12 . The nascent research in semiconductor spintronics emerged with the seminal proposal of a spin-based current modulator 22 , and was accelerated by the discovery of surprisingly long spin lifetimes at low tempera- tures under certain doping conditions 23 . Injection of spin-polarized current in hybrid ferromagnet-semiconductor systems at room temperature is being constantly improved 4–6 . Figure 1a shows the scheme of a universal magnetologic gate (MLG) set for the NAND operation; any binary logic function can be realized using a finite number of these gates. It consists of a semi- conductor layer beneath five elongated magnetic contacts with par- allel easy magnetization axes. We define fixed opposite directions as the binary states of ‘1’ and ‘0’, as shown in the figure. The operands of the logic operation are the magnetization directions of the contacts labelled by A, B, X and Y. Addressing a specific contact is facilitated by a matrix of current-carrying wires deposited on top of the structure (and/or below) that orient the magnetizations as in magnetic random access memory (MRAM) architectures 24,25 . The output of the gate is given by the current labelled by I M (t). This current is a transient response caused by rotating the magnetization of the middle contact, M. Below, we show a clear distinction between the current amplitude for ‘1’ and ‘0’ logic outputs. However, both output currents induce magnetic fields that are too small to write the magnetization direction of other contacts (cascading the output from a logic gate to the input of another). Attempting to amplify this current would lead to extreme power consumption when scaling-up the number of gates. Later, we will describe a circuit which avoids this problem. Figure 1b shows a closely related scheme in which a non-magnetic contact lies beneath the mid-section of the MLG. Here, the magnet- ization of M is pinned and I M (t) is triggered by applying a voltage signal (labelled by clk2) on the back-gate. We defer the discussion of this case to the end and proceed with the scheme shown in Fig. 1a. The MLG in Fig. 1a makes direct use of the distinction between the spin accumulation densities inside the semiconductor for the case of parallel or antiparallel alignment of two contacts at each side of the 1 Department of Physics, University of California San Diego, La Jolla, California 92093-0319, USA. x y z n-Type semiconductor X A M Y B C M C M V dd V dd V dd V dd a ‘1’ ‘0’ Insulator b X A M Y B clk2 I M (t) I M (t) Figure 1 | Design of the reprogrammable magnetologic gate. The inputs are the magnetization directions of the contacts labelled by A, B, X and Y. The general boolean expression of the gate is: OR(XOR(A,X),XOR(B,Y)). One may use the magnetization alignments of A and B to set different logic operations. For example, the figure shows a universal NAND operation between X and Y (A 5 B 5 ‘1’). a, Steady-state currents, driven by V dd , flow between A(B) and X(Y). The output is given by a transient current response, I M (t), caused by an in-plane single rotation of M. The amplitude of I M (t) is proportional to the spin accumulation in the semiconductor. In order to write the magnetization directions of the contacts in cascaded magnetologic gates, we first convert I M (t) to a binary voltage signal (see Fig. 3). This voltage signal will control the direction of a second, independent high-level current in wires on top of, and/or below, the contact(s) of other gate(s). b, A similar structure but with a pinned middle contact. The transient current, I M (t), is triggered by a voltage signal, clk2, applied to a (non-magnetic) back-contact beneath the mid-section. Semiconductor regions beneath the contacts are heavily doped. Vol 447 | 31 May 2007 | doi:10.1038/nature05833 573 Nature ©2007 Publishing Group