Analog Integrated Circuits and Signal Processing, 26, 141–156, 2001  C 2001 Kluwer Academic Publishers. Manufactured in The Netherlands. Low Voltage and Mismatch Analysis of Quadruple Source Coupled Multi-input Floating-gate Mosfet Multiplier with Offset Trimming CHEE YEE KWOK AND HAMID REZA MEHRVARZ School of Electrical Engineering, The University of New South Wales, Sydney, N.S.W. 2052, Australia. Tel: int+(612)-9385-5300 Fax: int+(612)-9385-5993 E-mail: cy.kwok@unsw.edu.au Received September 1, 1998; Revised January 27, 2000; Accepted February 7, 2000 Abstract. Considerations for optimisation of the MFMOS (Multi-input Floating-gate Mosfet) multiplier for gain, minimal total harmonic distortion, low supply voltage operation and offset trimming are considered in this paper. Analysis shows that good matching between pairs of devices are essential for low harmonic distortion. Results from simulation studies show that offset trimming can be facilitated by connecting the dc bias inputs in pairs and biasing them separately. A ±1.5 volt supply MFMOS multiplier has been designed and fabricated. Measured THD and nonlinearity at fullscale input are 0.8% and 0.5%, respectively. Bandwidth is more than 20 MHz and input dynamic range over a 0-1 MHz bandwidth is 92.6 db. The lowest measured operable supply voltage is ±0.9 volt. Key Words: analog multiplier, Floating-gate Mosfet, square-law I. Introduction Over the last decade, several four-quadrant analog mul- tipliers in Mosfet technology have been reported [1–13]. The reported techniques can be broadly di- vided into four categories: (1) Variable transconduc- tance technique [1,2] which is based on the Mosfet version of the Gilbert multiplier, (2) Voltage-controlled transconductance technique [3–5] using the I-V char- acteristic of Mosfets in the linear region, (3) Square- law technique [6–10], and (4) Linear transconductance technique [11–13] where a voltage controlled voltage to current converter is the core of the multiplier. For conventional applications, like modulation, demodu- lation, correlators, adaptive filters, frequency transla- tion, etc., good linearity, low distortion, wide input dynamic range and bandwidth are important. For neu- ral network systems [4,5,10] small device count, small area and low power consumption are most essential. Amongst the reported multipliers only some of them are operable at low supply voltage [9,12,14] which is mandatory for today’s widely used portable equip- ment, like mobile phones, cassette players and radio re- ceivers. Recently the authors reported a four-quadrant Mosfet analog multiplier using Multi-input Floating- gate Mosfet (MFMOS) devices [15], featuring very low harmonic distortion, excellent linearity characteristics for full scale input signal range equalling the supply voltage and input dynamic range of 95 dB. In this paper, the optimisation of the MFMOS mul- tiplier performance where constraints affecting over- all multiplier gain, harmonic distortion, offset voltage and low supply voltage operation are considered. Of- ten, these constraints produce conflicting outcomes. In section II, optimisation of the multiplier gain is con- sidered whilst maintaining a large input voltage range equalling the supply rail. Section III deals with de- sign considerations for low voltage operation. As de- vice mismatches have important ramifications on dis- tortion performance, identification of critical parameter mismatches and implications on circuit layout are con- sidered in section IV. Section V describes minor modi- fications to the circuit that could allow for trimming to reduce output offset voltage, harmonic distortion and linearity. The multiplier was fabricated using the MOSIS 2 µm double-poly double metal N-well CMOS process and the SPICE Level3 Mosfet parameters for simulation were supplied by MOSIS. In section VI, the results of the multiplier, operable at ±1.5 volts supply and below, are presented.