1736 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 29, NO. 11, NOVEMBER 2010 High-Level Synthesis for Designing Multimode Architectures Caaliph Andriamisaina, Philippe Coussy, Member, IEEE, Emmanuel Casseau, and Cyrille Chavet, Member, IEEE Abstract —This paper addresses the design of multimode ar- chitectures for digital signal and image processing applications. We present a dedicated design flow and its associated high-level synthesis tool, named GAUT. Given a unified description of a set of time-wise mutually exclusive tasks and their associated throughput constraints, a single register transfer level hardware architecture optimized in area is generated. In order to reduce the register, the steering logic, and the controller complexities, this paper proposes a joint-scheduling algorithm, which maximizes the similarities between the control steps and specific binding approaches for both operators and storage elements which max- imize the similarities between the datapaths. It is shown through a set of test cases that the proposed approach offers significant area saving and low-performance penalties compared to both state-of- the-art techniques and dedicated mono-mode architectures. Index Terms—Allocation, binding, high-level synthesis (HLS), multimode architectures, scheduling. I. Introduction E MERGING standards lead to an increasing demand for high performance, flexibility, and low-power embedded systems. These requirements have led to research on efficient devices to respect these constraints. On the one hand, the designer can use a pure software solution, which is extremely flexible and low cost. However, this solution does not system- atically offer good performances and low-power consumption. On the other hand, the hardwired solution, which consists of dedicated architectures (ASIC) and reconfigurables architec- tures such as field programmable gate arrays (FPGAs), can be used. FPGAs-based architectures provide partial reconfigura- tion at runtime but they still cannot achieve high performance (throughput, area, power consumption). Moreover, FPGAs often require too long reconfiguration time to switch rapidly the application’s architecture in a real-time context. ASICs are more suitable for high-performance systems, but they are much more complex to design and not flexible. Thus, to have a good tradeoff between flexibility and performance, addition Manuscript received November 18, 2009; revised March 19, 2010 and June 8, 2010; accepted June 24, 2010. Date of current version October 20, 2010. This paper was recommended by Associate Editor V. Narayanan. C. Andriamisaina was with the Lab-STICC Laboratory, Université de Bretagne-Sud, Lorient 56321, France. He is now with the Embedded Computing Laboratory, CEA Saclay, Gif-sur-Yvette 91191, France (e-mail: caaliph.andriamisaina@cea.fr). P. Coussy and C. Chavet are with the Lab-STICC Laboratory, Université de Bretagne-Sud, Lorient 56321, France (e-mail: philippe.coussy@univ-ubs.fr; cyrille.chavet@univ-ubs.fr). E. Casseau is with the French National Institute for Research in Computer Science and Control (INRIA/IRISA), University of Rennes 1, Lannion 22305, France (e-mail: emmanuel.casseau@irisa.fr). Digital Object Identifier 10.1109/TCAD.2010.2062751 of flexibility to dedicated architectures and/or improvement of software implementation performances have to be considered. The architectures that result from the addition of flexibility in hardwired architectures are named multimode architectures [1]. Multimode architectures are specifically designed for a set of time-wise mutually exclusive applications (multistandard applications). For example, a Viterbi decoder, typically used in a mobile system for the channel decoding part, has a constraint length k and a code rate R that can change from one communication standard to another requiring thus different architectures. In the global system for mobile communications standard k = 5 and R =1/2 while in the wireless local area network standard k = 7 and R =1/2 and in the 3G standard k = 9 and R =1/3 [2]. Multimode architectures can also be used to implement several application-specific instructions of configurable processors [3]. Based on high-level synthesis (HLS) techniques, we pro- pose, in this paper, a dedicated design flow and its associated HLS tool GAUT [4] to implement multimode architectures. The starting point is a C function wherein a set of time- wise mutually exclusive tasks can be specified through switch- case statements with their associated pragma (to define the associated throughput constraints). Then, these tasks are sorted to define the order in which they will be scheduled and bound. Next, the proposed scheduling and binding steps aim at reducing the cost in terms of memory (storage elements), steering logic (multiplexers), and decoding logic (FSM). Then, the number of both the registers and the multiplexers (Fig. 1) is optimized through a dedicated step. Finally, a multimode architecture that includes a single FSM and a shared datapath (a set of multiplexers, storage elements, and operators) is generated with its test-bench. This paper is organized as follows. Section II presents related work around multimode system design. Section III is dedicated to the problem formulation and Section IV in- troduces our design flow. Then, in Section V, we present in detail the method used to sort the tasks and in Section VI the resource allocation method. In Sections VII and VIII, we present the scheduling and the binding algorithms, respec- tively. Finally, experimental results are presented in Section IX and we conclude this paper in Section X. II. Related Work In order to design a multimode architecture, a designer, thanks to its knowledge and experience, can identify similar 0278-0070/$26.00 c  2010 IEEE