A single-electron XOR gate M.M. Dasigenis, I. Karafyllidis * , A. Thanailakis Department of Electrical and Computer Engineering, Democritus University of Thrace, GR-67100 Xanthi, Greece Received 8 September 2000; revised 3 October 2000; accepted 12 October 2000 Abstract A new single-electron circuit implementing the logic function XOR is presented in this paper. The logic gate proposed consists of five tunnel junctions, two capacitors and four islands. The operation of this gate is analysed using Monte Carlo simulation. The simulation results show that the gate operates in stable regions.  2001 Elsevier Science Ltd. All rights reserved. Keywords: Single-electron circuit; Logic gates 1. Introduction Single-electronics is a technology that makes possible the control of transport and position of individual electrons, utilizing the single-electron tunnelling phenomenon. The fundamental principle of single-electronics is the Coulomb blockade, which has been first observed and studied by Gorter [1]. Since then, it has seen a vast development because of the possibility of producing circuits that combine large scale integration and low power dissipation [2,3]. Several single-electron circuits have recently been proposed in the literature: single-electron memories [4], inverters and pumps [5], and majority gates [6]. The need for computer-aided analysis and design of single- electron circuits has long been recognized [7]. Several simulators have been implemented to support single-electron circuit design, based on the master equation, the Monte Carlo, and the simulated annealing methods [8–12]. A single-electron XOR gate is presented in this paper. The gate consists of five tunnel junctions, two capacitors and four islands, and has been designed and simulated using SIMON. SIMON is a single-electron circuit simulator and is based on a Monte Carlo method [10,11]. The stability plot of the gate shows that the gate operates in stable regions. 2. The single-electron XOR gate The single-electron XOR gate is shown in Fig. 1. The circuit consists of four islands N1–N4, and five tunnel junctions J1–J5. Tunnel junctions J2–J5 are identical. The resistance of each is 10 5 ohm and the capacitance is 10 -18 F. Tunnel junction J1 is less transparent in order to prevent electron transport from the ground (V ss ) to island N1 and vice versa. Its resistance and capacitance are 10 7 ohm and 10 -18 F, respectively. The voltage V dd is constant and its value is 0.1 V. V1 and V2 are the inputs to the XOR gate. V1 and V2 can take only two values, 0.0 V, which corresponds to the logic “1”, and -0.1 V, which corresponds to the logic “0”. The input voltages are applied to nodes N2 and N3, respectively, through the capacitors C1 and C2, which are identical, and their capacitance is 10 -18 F. The gate output is the island N1. The presence of a positive charge on this island corre- sponds to the logic “1”, whereas the absence of positive charge from it corresponds to the logic “0”. The operation of the XOR gate is shown in Fig. 2. Fig. 2a and b shows the time variation of input voltages V1 and V2, respectively. The inputs are piece-wise constant and apply all possible combinations of logic “0” and “1” to the gate. Fig. 2c shows the time variation of the charge Q1 at the output node N1. The charge at N1 is zero, when the input vector [0 0] is applied to the gate, it becomes positive, when the input vectors [1 0] and [0 1] are applied, and it becomes zero again when the input vector [1 1] is applied. The output transition from logic “0” to logic “1” and vice versa does not drive the gate to instability. A characteristic of the SIMON simulator is the possibility to calculate the current at the branches of the circuit. The calculation shows that during the output transition from logic “0” to logic “1” an electron is transported from N1 to V dd through junctions J3, J5, or through junctions J2, J4. The change in circuit free energy during the output transition from “0” to “1” has been calculated and the free energy Microelectronics Journal 32 (2001) 117–119 Microelectronics Journal 0026-2692/01/$ - see front matter  2001 Elsevier Science Ltd. All rights reserved. PII: S0026-2692(00)00126-9 www.elsevier.com/locate/mejo * Corresponding author. Tel.: +30-5417-9548; fax: +30-5412-9813. E-mail address: ykar@demokritos.cc.duth.gr (I. Karafyllidis).