A Comparative Study of Performance of AES Final Candidates Using FPGAs ⋆ Andreas Dandalis 1 , Viktor K. Prasanna 1 , and Jose D.P. Rolim 2 1 University of Southern California, Los Angeles CA 90089, USA {dandalis,prasanna}@halcyon.usc.edu http://maarcII.usc.edu 2 Centre Universitaire d’Informatique, Universit´ e de Gen` eve 24 Rue General Dufour, 1211 Gen` eve 4, Switzerland Jose.Rolim@cui.unige.ch Abstract. In this paper we study and compare the performance of FPGA-based implementations of the five final AES candidates (MARS, RC6, Rijndael, Serpent, and Twofish). Our goal is to evaluate the suit- ability of the aforementioned algorithms for FPGA-based implementa- tions. Among the various time-space implementation tradeoffs, we fo- cused primarily on time performance. The time performance metrics are throughput and key-setup latency. Throughput corresponds to the amount of data processed per time unit while the key-setup latency time is the minimum time required to commence encryption after providing the input key. Time performance and area requirement results are pro- vided for all the final AES candidates. To the best of our knowledge, we are not aware of any published results that include key-setup latency results. Our results suggest that Rijndael and Serpent favor FPGA implementations the most since their algorithmic characteristics match extremely well with the hardware characteristics of FPGAs. 1 Introduction The projected key role of AES in the 21st century cryptography led us to im- plement the AES final candidates using Field Programmable Gate Arrays (FP- GAs). The goal of this study is to evaluate the performance of the AES final candidates on FPGAs and to make performance comparisons. In addition, we evaluate the suitability of reconfigurable hardware as an alternative solution for AES implementations. In this study, we concentrate only on performance issues. We assume that all the considered algorithms are secure. Time performance and area requirements results are provided for all the final candidates. The time performance metrics are throughput and key-setup latency. Throughput corresponds to the amount of data processed per time unit while key-setup latency is the minimum time ⋆ This research was performed as part of the MAARCII project. This work is supported by the DARPA Adaptive Computing Systems program under contract no. DABT63- 99-1-0004 monitored by Fort Huachuca. C ¸.K. Ko¸c and C. Paar (Eds.): CHES 2000, LNCS 1965, pp. 125–140, 2000. c  Springer-Verlag Berlin Heidelberg 2000