Practical aspects Memory distribution: Techniques and practice for CAD applications Craig Chase * , Prakash Arunachalam, Jacob Abraham Electrical and Computer Engineering Department, The University of Texas, Austin, TX 78712, USA Received 14 April 1997; received in revised form 15 December 1997 Abstract We present a mechanism for exploiting the memory available in a network of workstations to run single-threaded, memory-bound applications. Such applications are common in the Computer Aided Design (CAD) area for integrated circuits. We experiment with two CAD applications and show that memory distribution enables these applications to process circuits that could not otherwise be processed. We achieve high locality of reference for applications with good temporal locality by using set-associative caches. To exploit spatial locality we utilized a technique called ``Distributed Object Traversal'' that transfers the thread of control to the process on which each object is stored (the converse operation to caching). Distributed object traversal is shown to provide excellent locality of reference for practical applications. The compound eect of the optimizations and integration of the memory distribution mechanism into the application provides ecient access to distributed memory. We compare our performance to that obtainable with the Treadmarks shared memory package and observe roughly 30% faster execution times for our system. Ó 1998 Published by Elsevier Science B.V. All rights reserved. Keywords: Workstation cluster; Memory distribution; Computer Aided Design (CAD); Partitioning load balance; Treadmarks; Caching 1. Introduction Although computational speedup is the most well known use of parallel com- puters, it is not the only potential justi®cation for using them. In this paper we consider using the collective memory available in a network of computers to solve Parallel Computing 24 (1998) 1597±1615 * Corresponding author. 0167-8191/98/$ ± see front matter Ó 1998 Published by Elsevier Science B.V. All rights reserved. PII: S 0 1 6 7 - 8 1 9 1 ( 9 8 ) 0 0 0 5 2 - 0