DESIGN OF A TURN-KEY 10 V PROGRAMMABLE JOSEPHSON VOLTAGE STANDARD SYSTEM P.D. Dresselhaus, M. Elsbury 1 , C.J. Burroughs, D. Olaya, S.P. Benz, N.F. Bergren, R. Schwall, and Z. Popovic 1 National Institute of Standards and Technology, Boulder, CO, USA 1 College of Engineering and Applied Science, University of Colorado, Boulder, CO, USA Abstract NIST is designing a 10 V Programmable Josephson Voltage Standard (PJVS) system with an improved microwave design and arrays of stacked Nb X Si 1-x -barrier Josephson junctions. For this new design a “ground-up” approach was used that takes into account all system issues in order to produce a robust 10 V system. By improving the uniformity of the microwave drive along the length of each array, constant-voltage steps with a larger current range are generated allowing the use of smaller critical current junctions. Smaller critical currents are important for lowering the total overall power dissipated on chip. Reducing power dissipation also increases the operating margins. Thus, all aspects of the design are interrelated and important for an optimized system. Introduction Voltage standards made with conventional super- conductor-insulator-superconductor (SIS) junctions have existed for many years [1-2], and more recently, PJVS 10 V systems have been fielded by PTB [3] and AIST [4]. The AIST PJVS circuit uses a 16 GHz microwave bias and 327 680 double-stacked NbN-NbTi x -NbN junctions. These normal-metal-barrier (SNS) junctions have the advantage of working at 10 K on a cryocooler. The PTB 10 V PJVS system is based on 69 120 SINIS junctions running at 70 GHz, which is compatible with conventional JVS microwave electronics. Unfortunately, both of these systems have been plagued by chips with low device yield and small operating current margins, typically less than 1 mA. In order to ensure noise immunity and robust operation, an easy-to-use, turnkey system should have large operating margins greater than 1 mA and high device yield. In pursuit of this goal, NIST has taken the stacked junction, filtered bias taps, and tapered transmission lines that were developed for the ac Josephson Voltage Standard system and applied them to a 10 V PJVS system design [5]. This “ground-up” approach also includes a complete redesign of every microwave component, including microwave dividers, bias taps, terminations, and transmission lines. System Design The schematic system design is shown in Fig. 1. A computer will control the overall system with simple commands to simplify the software and usability. The control electronics will have the bulk of the complexity, because it will interface with the computer and store information about the PJVS circuit, including information to control each array at the specified operating point. For simplicity, the initial circuit will be designed to produce only a small number of voltages to increase yield and avoid fine subdivision of the arrays. _____________________________________________________ *Contribution of the U.S. government, not subject to copyright. Fig. 1. 10V Turnkey system design. The computer interface will send and receive simple commands via a standard interface. Packaging Because users of voltage standards currently work at 4 K, the system is designed to work either in liquid helium or on a 4 K cryocooler. An operating frequency in the range 15 GHz to 25 GHz has been chosen, so as to be compatible with low-cost microwave sources and amplifiers. This leads to a junction count N of at least 200,000 junctions in order to reach 10 V. The amount of heat that needs to be dissipated in the circuit determines the thermal packaging requirements. This heat load is of the order 10 V * I c , where I c is the junction critical current. As a trade-off between increasing the thermal load and decreasing the operating margins, critical currents of 6 mA will be used for the junctions, which is about half that of our previous designs. This should reduce the heat load to approximately 100 mW, which has recently been demonstrated for 5 V PJVS chips on the cold stage of a cryocooler. Because the standard NIST 1 cm x 1 cm chip size is too small to contain the large number of junctions, a chip size of 17 mm x 12 mm, has been chosen (which is also the maximum field size of our i-line stepper). The larger size will also increase the heat flow out of the substrate. Heat-sinking of the backside of the chip to a copper plate is accomplished with indium foil and applied pressure. Josephson Junctions Recent advances in Josephson junction technology at NIST have led to a focus on amorphous Nb x Si 1-x -barrier junctions with Nb superconducting electrodes. These junctions have the dual advantages of (1) using the Nb content x of the barrier to tune the junctions from SIS behavior (small x) to SNS behavior (x ~0.12); and (2) having a well-defined process to fabricate stacks of three (or higher) junctions, which increases the junction count without increasing the chip size. Unfortunately, our operating margins currently decrease for stacks taller than three junctions, but we are working to understand this issue. Having chosen the critical current to be 6 mA, the remaining junction parameter is the normal-state junction resistance R n which also sets the characteristic frequency of the system, f c = I c R n K J , where K J is the Josephson constant. There is a trade-off in choosing R n between increasing f c , and thus the voltage per junction, and increasing the dissipation of the array. Dissipation limits the number of junctions per array to N z ≈ Z 0 /R n , where Z 0 is the characteristic impedance of the transmission line.