Towards a framework for designing applications onto hybrid nano/CMOS fabrics Catherine Dezan a,Ã , Ciprian Teodorov a , Loı¨c Lagadec a , Michael Leuchtenburg b , Teng Wang b , Pritish Narayanan b , Andras Moritz b a LAB-STICC UMR 3192, Universite´ de Bretagne Occidentale, France b Electrical and Computing Engineering Department, University of Massachusetts at Amherst, USA article info Article history: Received 27 February 2008 Accepted 31 July 2008 Keywords: CAD tool Nanotechnology Fault tolerance abstract The design of CAD tools for nanofabrics involves new challenges not encountered with conventional design flow used for CMOS technology. In this paper, we propose to define a new framework able to help the designer to map an application on a wide range of emerging nanofabrics. Our proposal is based on a variety of models that capture as well as isolate the differences between these fabrics. This tool supports the design flow starting from behavioral description up to final layout. It integrates fault-tolerant techniques and fabric-related density transformations with more conventional design automation techniques. After an overview of common requirements, physical models, and associated techniques, a case study in the context of NASIC fabrics is used to illustrate some of the concepts. & 2008 Elsevier Ltd. All rights reserved. 1. Introduction As an alternative to CMOS based designs, novel nanofabrics are being proposed based on a combination of lithographic processes and bottom-up self-assembly based manufacturing. These fabrics include NanoPLA [1,2], CMOL [3], FPNI [4], and NASIC [5]—to name a few. They are based on a variety of devices such as FETs, spin-based devices, diodes, and molecular switches. Furthermore, all these architectures include some support in CMOS: some like FPNI would move the entire logic into CMOS, others, like NASIC, would only provide the control circuitry in CMOS. The rationale for this varies but includes targeted application areas as well as manufacturability issues. Other differences include fault handling: e.g., some proposals would use reconfigurable approaches, while others like NASICs would rely on built-in techniques based on redundancy, voting, error correction, and/or unique fabric structures. The architectures proposed range from general purpose processors to program- mable logic arrays similar to FPGAs, and to more specialized devices such as cellular arrays and cellular neural networks. In order to implement an application on a nanofabric, specific tools are already proposed by the respective research groups [1,5,6] as CAD tools are necessary to be able to design and evaluate the capabilities of larger-scale systems. As the underlying technologies are still evolving according to advances in devices, manufacturing, and fabric structures, CAD tools for nanofabrics should be made, ideally generic enough to integrate added features or to enable new paradigms as well as comparison between various approaches. This paper proposes a prototyping CAD tool that considers an explicit specification of the underlying nanofabric. It extends the classical design flow—shown in the Fig. 1—for designing an application from behavioral specifications (e.g., in VHDL, Verilog, or SystemC) onto physical designs. It is based on a range of trans- formations applied at different levels of description/abstraction of the application/problem that is mapped. The new design flow proposed incorporates a variety of models associated with the nanofabric to allow optimizations to occur on generic data structures. Through a computational model, an architectural model, a technological model, and a fault model key aspects of a particular fabric can be captured and abstracted. The proposed models interact with the behavioral and the physical tools to produce an abstract layout for the design— starting from a high-level description. Parts that are mapped to nanoscale are separated from parts that use conventional CMOS technology. Nanoscale fabrics under consideration have the following features:  The use of self-assembly based manufacturing techniques, e.g., nanopatterning, fluidic alignment, DNA-based self-assembly, ARTICLE IN PRESS Contents lists available at ScienceDirect journal homepage: www.elsevier.com/locate/mejo Microelectronics Journal 0026-2692/$ - see front matter & 2008 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2008.07.072 Ã Corresponding author. Tel.: +33 2 98 0169 73. E-mail addresses: catherine.dezan@univ-brest.fr (C. Dezan), ciprian.teodorov@univ-brest.fr (C. Teodorov), loic.lagadec@univ-brest.fr (L. Lagadec), mleuchte@ecs.umass.edu (M. Leuchtenburg), twang@ecs.umass.edu (T. Wang), pnarayanan@ecs.umass.edu (P. Narayanan), andras@ecs.umass.edu (A. Moritz). Microelectronics Journal ] (]]]]) ]]]–]]] Please cite this article as: C. Dezan, et al., Towards a framework for designing applications onto hybrid nano/CMOS fabrics, Microelectron. J (2008), doi:10.1016/j.mejo.2008.07.072