Hardware Implementation of a 32-bit Fault Tolerant ALU Design using (63,57) BCH Code Vahid Khorasani Department of electrical engineering Sharif University of Technology International campus Tehran, Iran Bijan Vosoughi Vahdat Department of electrical engineering Sharif University of Technology Tehran, Iran vahdat@sharif.edu Mohammad Mortazavi Department of electrical engineering Sharif University of Technology International campus mortazavi@sharif.edu khorasani_vahid@kish.sharif.ir Abstract—In recent years, security and reliable data has become very important in many transmission applications. In this paper, we present a new 32-bit ALU (Arithmetic and Logic Unit) design that is secure against any fault attacks. The designed ALU is capable of correcting any single error in any position of its 32- bits input registers of ALU. For this reason, we take into account of the BCH (Bose, chaudhuri, and Hocquenghem) encoder and decoder using the prototyping FPGA (Field Programmable Gate Array). Since the usages of the ARM processors are more applicable for control system, we give the fault tolerance characteristic through the error control coding to this processor. As a result, the core for implementation of an ALU employing BCH code on Spartan-3 FPGA has been provided. The reliability of system is high relative to other works that is exist in the literature. Index Terms—Fault tolerant, ALU, BCH codes, Encoding, Decoding, FPGA. I. INTRODUCTION ystem reliability is one of major issues in embedded processors designs for space application such as satellite, military, communications etc. Various attacks exist in space on integrated circuits that comes from sun activity [1]. Such as solar rays which are composed of charged particles. The radiation from sun effects in integrated circuits causes digital damage and upsets such as SEU (Single Event Upset), SET (Single Event Transient) and etc as presented in [2]. Such attacks can upset either combinational logic or sequential logic in other words a bit flip can occur in memory or register bits and this may cause the mission of system would be completely act differently. For above reasons fault tolerant technique is used to keep integrated circuits against such attacks in space. Our goal is that to overcome these difficulties designing a new 32-bit ALU that is resistance against these any faults and able to correct any one bit fault in any position of its 32 bits input register of ALU. Apart from many applications of such work one considerable for us is the application in on board computer (OBC) of a satellite. There are many design-based techniques to give the fault tolerant scheme such as detection techniques and mitigation techniques. Detection technique consists of hardware redundancy, time redundancy and information redundancy scheme and mitigation techniques consists of TMR (triple modular redundancy), multiple redundancy with voting as presented in [3], and EDAC (error detection and correction coding) scheme. Hardware redundancy (HR) is based on extra component that can be composed of extra same circuit to perform the same operation at the same time. In this way the faults can be identified by duplication or masked by triplication and then by comparing the outputs through a voter. Error detection and correction codes can also be type of hardware redundancy due to the requirements of extra bits that is able to detect and correct errors. Thus it consumes 100% hardware overhead with high fault coverage. The proposed technique will to identify an SEU in the sequential logic. The time redundancy (TR) consists of extra execution time with sampling at different time then comparing results to detect errors this technique are usually utilized to detect a SET in the combinational logic and also it requires lower hardware overhead than the HR and EDC. However this method has a major drawback due to the extra delay during recompilation. The information redundancy is based on EDC (error- detection code). This technique also requires extra hardware however it gives a low hardware overhead than the HR. Thus this method can be considered as a good choice to meet our criteria. The previous work has used ALU to keep safe from logic and arithmetic operation such as: Parity code, Residue code [4], Berger code [5], etc. The TMR (triple modular redundancy) technique uses three components. In fact, the entire device triplicate to fault masking by a single voter then the voter gives the correct value in the presence of an upset by the majority opinion as an output. Similar to previous techniques, needs extra logic. It corrects up to three faults per 3-bit word, if each fault is placed in a distinct bit. This technique votes the true value but it doesn't correct it. In addition faults will accumulate, if there is no additional device to correct them. Hence this approach is also more applicable to space applications. Error detection and correction (EDAC) codes technique is usually utilized to mitigate SEU in integrated circuit and it requires extra hardware. Nevertheless this technique gives strongly faults coverage. Hence, we are considering this technique to cover our goals. EDAC codes can be implemented in two ways and it depends on transmission data. If error control system can transfer data in two-direction where the receiver detects an error in a data frame, it automatically requests the transmitter to resend the data frame. S